This patch introduces support of new boards with ARC cores.
[1] Synopsys SDP board
This is a new-generation development board from Synopsys that
consists of base-board and CPU tile-board (which might have a real
ASIC or FPGA with CPU image).
It sports a lot of DesignWare peripherals like GMAC, USB, SPI, I2C
etc and is intended to be used for early development of ARC-based
products.
[2] nSIM
This is a virtual board implemented in Synopsys proprietary
software simulator (even though available for free for open source
community). This board has only serial port as a peripheral and so
it is meant to be used for runtime testing which is especially
useful during bring-up of new tools and platforms.
What's also important ARC cores are very configurable so there're
many variations of options like cache sizes, their line lengths,
additional hardware blocks like multipliers, dividers etc. And this
board could be used to make sure built software still runs on
different HW configurations.
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
SVN-Revision: 47589
Support is present in 3.19 and above as kernel commit:
fcc87a95195236b0935183361a72e4a98bf577d8
Changes to other existing patches are a result of "make target/linux/refresh".
Signed-off-by: Srdjan Rosic <srdjan.rosic@gmail.com>
Signed-off-by: Srdjan Rosic <rosic@google.com>
SVN-Revision: 47588
I accidentally deactivated it. This should be set to active it in any case
independently what was set in the user config.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 47587
* use kernel buildin transfer_one_message. we only need to implement
transfer_one and set_cs function
* should support use gpio as cs pin
* deselected the spi device when setup and add debug info
* only reset device when first driver probe
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47579
before spi transfer. use spi_prepare_message to setup spi hardware. it
will setup MSB, spi mode and speed
remove sys_freq member and speed check code
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47578
* check clock rate, SPI mode, and word sizes
* setup spi polarity
* enable spi1 hw if need
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47577
* fill struct according to the member order
* add error clean up
* set min/max spi speed. so we don't need to check again
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47576
use loops_per_jiffy, spi clock speed and write bytes to get the
spi loop count. if loop to 0 than spi operation timeout.
remove usleep. we only write 1 byte to spi device. use busy loop
would be better.
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47575
This patch adds the posibility to config the led behaviour of the lantiq phys
over the devicetree bindings.It patches the 0023-NET-PHY-adds-driver-for-lantiq-PHY11G
for 3.18 and 4.1. I have also added a register description overview for
applicable values. This goes to the documentation folder in the linux kernel.
Signed-off-by: Florian Eckert <Eckert.Florian@googlemail.com>
SVN-Revision: 47566
It turned out that mtk_nand driver uses some sophisticated accounting and a
general nand code must be patched.
This patch adds required read and erase calls to a general nand code. I
used a code for re6500 released by Linksys as a reference.
All required operations (erase, write and read) are usable. However I found
that jffs2 filesystem can be created only on top of a ubi volume. I tried
to create jffs2 directly on mtd device but pages with clean markers are
became uncorrectable.
Signed-off-by: Kirill Berezin <fyiwdt@gmail.com>
SVN-Revision: 47565
All RTC drivers require the kernel to be built with CONFIG_RTC_CLASS=y.
Set it accordingly.
Tested only with DS1307.
Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
SVN-Revision: 47564
This patch improves the default configuration of DWC2 on lantiq SoCs
somewhat:
* Set maximum packet count to largest allowed value by the DWC2 (511)
* Use 16-bit DMA bursts
* Divide fifo buffers more evenly
Default fifo buffer sizes from original ltq-hcd driver seem really
irrational. For example according to DWC2 data book rxfifo size of 240
will not fit even a single full length USB packet. On the other hand
non-periodic tx fifo size of 240 is more than enough to fit one complete
packet.
Change the sizes around to improve the situation and to fix some issues
especially with isochronous USB transfers.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
SVN-Revision: 47563
The hwid check was wrong, causing the AR71XX_MODEL value to end with a
space (as $hwver was unset).
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
SVN-Revision: 47553
r47218 was missing needed changes which were accidentally
ommitted from the patch.
This should fix#20878
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 47552
