6 commits

Author	SHA1	Message	Date
John Crispin	87df7da757	ramips: Fix MT7621 pinmux bits for uart3, uart2, mdio ... The MT7621 uses a 2 bit wide configuration of the sdhci, spi, mdio, pcie, wdt, uart2 and uart3 in the GPIO_MODE register. It was correctly done for sdhci, spi, pcie and wdt, The same has to be done for uart3, uart2 and mdio. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 46645	2015-08-17 06:15:49 +00:00
John Crispin	09851afd33	ramips: Fix amount of MT7621 pins controlled by spi group ... The PINS conntrolled by the SPI bits in the GPIO_MODE register is always 7 and not 8 for nand mode. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 46644	2015-08-17 06:15:44 +00:00
John Crispin	9ed654e389	ramips: Fix uart2/uart3 pinmux order on MT7621 ... The uart3 setting in GPIO_MODE register is before the uart2 setting. Also don't mix uart2 and uart3 function/groups. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 46643	2015-08-17 06:15:34 +00:00
Jonas Gorski	76d079204d	kernel: update 3.18 to 3.18.14 ... Changelogs: * https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.12 * https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.13 * https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.14 Build tested on brcm63xx and ipq806x, runtested on brcm63xx. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 45711	2015-05-21 19:32:46 +00:00
John Crispin	44b929fcdd	ralink: make the mt7621 irq core with with the new CM api ... Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44418	2015-02-12 08:07:39 +00:00
John Crispin	654bc380ec	ralink: add 3.18 support ... keep default as 3.14, mt7621 gic need to be ported to 3.18 Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44349	2015-02-09 12:13:55 +00:00