ralink: make the mt7621 irq core with with the new CM api
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44418
This commit is contained in:
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de8d6e447c
commit
44b929fcdd
2 changed files with 62 additions and 30 deletions
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@ -2,9 +2,11 @@ CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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# CONFIG_ARCH_HAS_SG_CHAIN is not set
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_BOARD_SCACHE=y
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@ -26,11 +28,13 @@ CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_MIPSR2_IRQ_EI=y
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CONFIG_CPU_MIPSR2_IRQ_VI=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_MSA=y
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CONFIG_CSRC_R4K=y
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CONFIG_DEBUG_PINCTRL=y
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CONFIG_DMA_NONCOHERENT=y
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@ -44,7 +48,6 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_NET_UTILS=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GPIOLIB=y
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@ -55,12 +58,14 @@ CONFIG_GPIO_SYSFS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAS_IOPORT_MAP=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_BPF_JIT=y
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CONFIG_HAVE_CC_STACKPROTECTOR=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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@ -69,11 +74,11 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_KVM=y
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@ -95,19 +100,21 @@ CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_GIC=y
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CONFIG_IRQ_WORK=y
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CONFIG_KERNFS=y
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CONFIG_LIBFDT=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MIPS=y
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CONFIG_MIPS_CM=y
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CONFIG_MIPS_CMP=y
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CONFIG_MIPS_CPU_SCACHE=y
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CONFIG_MIPS_GIC_IPI=y
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=6
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CONFIG_MIPS_L1_CACHE_SHIFT_6=y
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# CONFIG_MIPS_MACHINE is not set
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CONFIG_MIPS_MT=y
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# CONFIG_MIPS_MT_DISABLED is not set
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CONFIG_MIPS_MT_FPAFF=y
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CONFIG_MIPS_MT_SMP=y
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# CONFIG_MIPS_MT_SMTC is not set
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# CONFIG_MIPS_O32_FP64_SUPPORT is not set
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CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
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# CONFIG_MIPS_VPE_LOADER is not set
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@ -115,10 +122,10 @@ CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MT7621_WDT=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_SEAMA_FW=y
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CONFIG_MTD_SPLIT_SUPPORT=y
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CONFIG_MTD_SPLIT_TRX_FW=y
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CONFIG_MTD_SPLIT_UIMAGE_FW=y
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CONFIG_NEED_DMA_MAP_STATE=y
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@ -128,9 +135,11 @@ CONFIG_NET_RALINK_GSW_MT7620=y
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CONFIG_NET_RALINK_MDIO=y
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CONFIG_NET_RALINK_MT7620=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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# CONFIG_NO_IOPORT_MAP is not set
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CONFIG_NR_CPUS=4
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS_PCI=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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@ -146,16 +155,18 @@ CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PHYLIB=y
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# CONFIG_PINCONF is not set
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# CONFIG_PHY_RALINK_USB is not set
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_RT2880=y
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# CONFIG_PINCTRL_SINGLE is not set
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_GPIO=y
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# CONFIG_POWER_RESET_GPIO_RESTART is not set
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# CONFIG_POWER_RESET_LTC2952 is not set
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# CONFIG_POWER_RESET_SYSCON is not set
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CONFIG_POWER_SUPPLY=y
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# CONFIG_PREEMPT_RCU is not set
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CONFIG_RALINK=y
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CONFIG_RALINK_USBPHY=y
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# CONFIG_RALINK_WDT is not set
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RESET_CONTROLLER=y
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@ -188,21 +199,16 @@ CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_SYS_SUPPORTS_MIPS16=y
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CONFIG_SYS_SUPPORTS_MIPS_CMP=y
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CONFIG_SYS_SUPPORTS_MULTITHREADING=y
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CONFIG_SYS_SUPPORTS_SCHED_SMT=y
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CONFIG_SYS_SUPPORTS_SMP=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TREE_RCU=y
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# CONFIG_USB_EHCI_HCD is not set
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CONFIG_USB_MT7621_XHCI_PLATFORM=y
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CONFIG_USB_PHY=y
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CONFIG_USB_SUPPORT=y
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# CONFIG_USB_UHCI_HCD is not set
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CONFIG_USB_XHCI_PLATFORM=y
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_WEAK_ORDERING=y
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CONFIG_XPS=y
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CONFIG_ZONE_DMA_FLAG=0
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# CONFIG_MTK_MTD_NAND is not set
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@ -78,7 +78,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#endif
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--- a/arch/mips/kernel/vmlinux.lds.S
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+++ b/arch/mips/kernel/vmlinux.lds.S
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@@ -51,6 +51,7 @@ SECTIONS
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@@ -51,6 +51,7 @@
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/* read-only */
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_text = .; /* Text and read-only data */
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.text : {
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@ -88,7 +88,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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LOCK_TEXT
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -7,6 +7,11 @@ config CLKEVT_RT3352
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@@ -7,6 +7,11 @@
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select CLKSRC_OF
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select CLKSRC_MMIO
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@ -100,7 +100,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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choice
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prompt "Ralink SoC selection"
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default SOC_RT305X
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@@ -28,6 +33,15 @@ choice
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@@ -28,6 +33,15 @@
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config SOC_MT7620
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bool "MT7620"
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@ -116,7 +116,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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endchoice
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choice
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@@ -59,6 +73,10 @@ choice
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@@ -59,6 +73,10 @@
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depends on SOC_MT7620
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select BUILTIN_DTB
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@ -154,7 +154,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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--- a/arch/mips/ralink/Platform
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+++ b/arch/mips/ralink/Platform
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@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
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@@ -27,3 +27,8 @@
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#
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load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
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cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
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@ -165,7 +165,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
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--- /dev/null
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+++ b/arch/mips/ralink/irq-gic.c
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@@ -0,0 +1,271 @@
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@@ -0,0 +1,268 @@
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+#include <linux/init.h>
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+#include <linux/sched.h>
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+#include <linux/slab.h>
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@ -185,9 +185,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#include <asm/setup.h>
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+
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+#include <asm/gic.h>
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+#include <asm/gcmpregs.h>
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+
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+#include <asm/mach-ralink/mt7621.h>
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+#define GIC_BASE_ADDR 0x1fbc0000
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+
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+unsigned long _gcmp_base;
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+static int gic_resched_int_base = 56;
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@ -241,7 +241,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ gic_intr_map[i].pin = GIC_CPU_INT0;
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+ gic_intr_map[i].polarity = GIC_POL_POS;
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+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
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+ gic_intr_map[i].flags = GIC_FLAG_IPI;
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+ gic_intr_map[i].flags = 0;
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+ }
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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@ -388,11 +388,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ if (!_gcmp_base)
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+ panic("Failed to remap gcmp memory\n");
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+
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+ if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
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+ panic("Failed to find gcmp core\n");
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+
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+ /* tell the gcmp where to find the gic */
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+ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
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+ write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
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+ gic_present = 1;
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+ if (cpu_has_vint) {
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+ set_vi_handler(2, gic_irqdispatch);
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@ -523,7 +520,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+}
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--- /dev/null
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+++ b/arch/mips/ralink/mt7621.c
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@@ -0,0 +1,183 @@
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@@ -0,0 +1,192 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@ -539,10 +536,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <asm/gcmpregs.h>
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+
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+#include <asm/mipsregs.h>
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+#include <asm/smp-ops.h>
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+#include <asm/mips-cm.h>
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+#include <asm/mips-cpc.h>
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+#include <asm/mach-ralink/ralink_regs.h>
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+#include <asm/mach-ralink/mt7621.h>
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+
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+
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+ rt2880_pinmux_data = mt7621_pinmux_data;
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+
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+ if (register_cmp_smp_ops())
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+ panic("failed to register_vsmp_smp_ops()");
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+ /* Early detection of CMP support */
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+ mips_cm_probe();
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+ mips_cpc_probe();
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+
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+ if (!register_cps_smp_ops())
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+ return;
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+ if (!register_cmp_smp_ops())
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+ return;
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+ if (!register_vsmp_smp_ops())
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+ return;
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+}
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--- a/arch/mips/kernel/mips-cm.c
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+++ b/arch/mips/kernel/mips-cm.c
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@@ -105,7 +105,7 @@
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write_gcr_base(base_reg);
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/* disable CM regions */
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- write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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+/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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@@ -113,7 +113,7 @@
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write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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-
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+*/
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/* probe for an L2-only sync region */
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mips_cm_probe_l2sync();
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