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50 commits

Author SHA1 Message Date
David Bauer
abb4ab076f ar71xx: fix incorrect speed setting on QCA9556
The QCA9556 only has a SGMII interface. However the speed on the
ethernet link is set for the non-existant xMII interface.

This commit fixes this behavior.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-06-18 23:23:30 +02:00
David Bauer
b6a4c67468 ar71xx: add support for Fritz!Box 4020
This commit adds support for the AVM Fritz!Box 4020 WiFi-router.

SoC:   Qualcomm Atheros QCA9561 (Dragonfly) 750MHz
RAM:   Winbond W971GG6KB-25
FLASH: Macronix MX25L12835F
WiFi:  QCA9561 b/g/n 3x3 450Mbit/s
USB:   1x USB 2.0
IN:    WPS button, WiFi button
OUT:   Power LED green, Internet LED green, WLAN LED green,
       LAN LED green, INFO LED green, INFO LED red
UART:  Header Next to Black metal shield
       Pinout is 3.3V - RX - TX - GND (Square Pad is 3.3V)
       The Serial setting is 115200-8-N-1.

Tested and working:
 - Ethernet (LAN + WAN)
 - WiFi (correct MAC)
 - Installation via EVA bootloader
 - OpenWRT sysupgrade
 - Buttons
 - LEDs

Not working:
 - USB port

Installation via EVA:
In the first seconds after Power is connected, the bootloader will
listen for FTP connections on 169.254.157.1 (Might also be 192.168.178.1). Firmware can be uploaded
like following:

  ftp> quote USER adam2
  ftp> quote PASS adam2
  ftp> binary
  ftp> debug
  ftp> passive
  ftp> quote MEDIA FLSH
  ftp> put openwrt-sysupgrade.bin mtd1

Note that this procedure might take up to two minutes. After transfer is
complete you need to powercycle the device to boot OpenWRT.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-05-07 10:42:26 +02:00
Felix Fietkau
f62d2b9549 ar71xx: remove pdata->fifo_cfg*
The values are the same for all chipsets that use it

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2018-03-04 19:37:20 +01:00
Vittorio Gambaletta
d40a358136
ag71xx: Fix rx ring buffer stall on small packets flood on qca956x and qca953x.
Backported from Code Aurora QSDK

Signed-off-by: Vittorio Gambaletta <openwrt@vittgam.net>
2017-12-29 15:17:07 +01:00
Felix Fietkau
72327d1757 ar71xx: fix ethernet PLL configuration for QCA956x
QCA956x is configured like AR934x, not like the older chips.
Should fix ethernet hangs when using the WAN port without SGMII

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2017-02-17 12:16:13 +01:00
Henryk Heisig
eec0c41375 ar71xx: QCA956X: add missing register
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
2017-01-26 11:38:20 +01:00
Felix Fietkau
83997146e7 ar71xx: disable flow control to the built-in switch on AR934x
It apparently causes a regression on some devices if the ethernet cable
is plugged in while booting.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-08-25 11:54:31 +02:00
Felix Fietkau
be08fdd007 ar71xx: disable pdata->use_flow_control for QCA9558
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-06-27 12:12:40 +02:00
Felix Fietkau
75b2105cd3 ar71xx: rename ethernet pdata->builtin_switch to use_flow_control
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-06-27 12:12:40 +02:00
Felix Fietkau
26b8db2537 ar71xx: enable flow control for ethernet MACs with built-in switch
Should fix LAN speed issues on some devices. This is an updated version
of the previously reverted commit with the same name.
It improves the check for MACs connected to a built-in switch

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-06-26 11:21:17 +02:00
Felix Fietkau
5b34dffcbd ar71xx: fix DDR write buffer flushing issues with 4.4
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-05-15 20:55:39 +02:00
John Crispin
58143e9b65 Revert "ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg"
Not all mach-* files set all boards correctly in ETH_CFG. They depend on
some preset values by u-boot which were not previously modified by
ath79_setup_qca955x_eth_cfg. Avoiding to modify them in this function keeps
it backward compatible for these boards.

This reverts commit 119b8ab2c2eac237ec4e9c4d0ed53df22b5c6978.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49072
2016-03-23 12:52:20 +00:00
John Crispin
b269a3520d Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x"
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.

This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49071
2016-03-23 12:52:17 +00:00
John Crispin
22c5f96c6b ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x
Some u-boot versions for QCA955x change the delays based on the link speed
during boot. This usually breaks the support of other linkspeeds when
OpenWrt is booted. It also conflicts with the
at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own
values in QCA955X_GMAC_REG_ETH_CFG.

The default RGMII values from the Atheros u-boot are currently used to
preset the existing mach files. These may have to be adjusted for boards
using different values but which are not currently set them explicitely in
OpenWrt.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Christian Beier <cb@shoutrlabs.com>
Cc: Chris R Blake <chrisrblake93@gmail.com>
Cc: Benjamin Berg <benjamin@sipsolutions.net>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
Cc: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Dirk Neukirchen <dirkneukirchen@web.de>
Cc: Christian Mehlis <christian@m3hlis.de>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 49029
2016-03-16 09:27:08 +00:00
John Crispin
be68f34708 ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg
Some u-boot versions for QCA955x set currently not cleared bits depending
on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c
file is responsible to select the correct configuration bits and thus the
ath79_setup_qca955x_eth_cfg has to clear the unset.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49028
2016-03-16 09:27:04 +00:00
Felix Fietkau
4802f611cb ar71xx: fix qca956x ethernet initialization
Complete internal switch initialization for QCA956X.
Set default mdio device if the interface mode of GE0 is not SGMII (fix ticket ).

Signed-off-by: Weijie Gao <hackpascal@gmail.com>

SVN-Revision: 48937
2016-03-07 08:45:01 +00:00
Felix Fietkau
a63fd6faf7 ar71xx: fix MDIO bus probe on QCA956x
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 48651
2016-02-07 21:00:01 +00:00
Felix Fietkau
a5dd378a0e ar71xx: fold patch 622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch into files/
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 48650
2016-02-07 20:59:51 +00:00
John Crispin
f6607a4bec ath79: dev-eth: fix QCA9561 set phy interface mode and mask
QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different
is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they
have the same device ID(0x1150). So they share the same codes.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>

SVN-Revision: 46971
2015-09-16 08:33:04 +00:00
Felix Fietkau
c9e433206f ar71xx: rework patch for qca953x/956x
Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e

Changelist,
    - add more register defines
    - add EHCI support
    - fix GPIO pin count to 18
    - fix chained irq disabled
    - fix GMAC0/GMAC1 initial
    - fix WMAC irq number to 47
    - merge the changes of dev-eth.c from the patch to file.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

SVN-Revision: 46207
2015-07-07 08:05:55 +00:00
Felix Fietkau
f4e6418a32 ar71xx: add a helper function to set RXDV/RXD of ETH_CFG on AR934x
The ETH_RXDV_DELAY (17:16) and ETH_RXD_DELAY (15:14) are currently not cleared
by the function ath79_setup_ar934x_eth_cfg. Clearing these in the
ath79_setup_ar934x_eth_cfg may cause problems on some hardware because they
rely on the preset value by the bootloader.

Instead another function is introduced which also works on ETH_CFG on AR934x.
It can be used to safely clear and set ETH_RXDV_DELAY and ETH_RXD_DELAY on
machines which require special settings.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 45523
2015-04-20 15:00:52 +00:00
John Crispin
3572657c5a ar71xx: dev-eth: replace mdelay calls
Similar to patch 2. Replace further mdelay calls.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

SVN-Revision: 43540
2014-12-07 16:53:15 +00:00
Felix Fietkau
60b81acd60 ath79: dev-eth: Don't advertise 1gbit in link code word on ar9331
While the AR9331 has a gigabit MAC towards the internal switch, the
integrated PHYs however are only 100-base-tx capable.  The existing code
however advertieses gigabit capability in the link status word.  If you
attach such a PHY to a gigabit capable switch on the remote end, with
some probability it attempts to negotiate gigabit and fails, falling
baco to the AR9331 assuming a 10mbit half-duplex link.  This has been
observed quite frequently with the Carambola2 and gigabit capable
switches.

In ath79_register_eth(), "pdata->has_gbit = 1;" is set unconditionally
for both AR9331 ethernet ports. This is most likely wrong. Despite the
two MAC IP cores being gigabit MACs, the MAC for eth1 is connected to a
100base-T PHY via MII. The has_gbit attribute is used in the ethernet
driver to determine the supported link modes.

So either pdata->has_gbit is not set to 1 anymore, or the ethernet
driver needs to be modified to determine the advertised link code word
on another criteria than pdata->has_gbit.  This patch implements the
former solution.

Signed-off-by: Harald Welte <laforge@gnumonks.org>

SVN-Revision: 42432
2014-09-07 09:45:32 +00:00
Gabor Juhos
ee3dfafaf1 ar71xx: add a helper function for setting up ETH_CFG register on QCA955x
Signed-off-by: Jon Suphammer <jon@suphammer.net>
Patchwork: http://patchwork.openwrt.org/patch/5839/
[juhosg: fix coding style]
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 41623
2014-07-13 19:43:56 +00:00
Felix Fietkau
f80f0c7d22 ar71xx: add support for QCA953x SoC
I don't have access to the specs, so I'm not sure about every detail, but I
haven't seen any problems with my test system, a TL-WR841N v9. It looks pretty
much like a QCA955x without PCI, a little twist in the clock calculation and
a AR9331-compatible switch.

Features not yet supported:

* EHCI (my test system doesn't have USB)
* ? (I have no idea if the QCA953x has any other features I don't know about
that aren't used by the TL-WR841N v9)

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

SVN-Revision: 40399
2014-04-07 07:59:45 +00:00
Gabor Juhos
05f8604e2e ar71xx: fix max frame length of the QCA955x SoCs
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39161
2013-12-23 17:05:23 +00:00
Gabor Juhos
76f37c5d46 ar71xx: don't set builtin_switch flag for QCA9558
It makes no sense, the SoC has no built-in switch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39160
2013-12-23 17:05:21 +00:00
Gabor Juhos
f2cd3399f7 ar71xx: allow to use large ethernet frames on AR934x SoCs
The hardware supports large ethernet frames. Override
the maximum frame length and packet lenght mask in the
platform data to allow to use large MTU on the ethernet
interfaces.

Limit the feature to AR934x SoCs for now. It should work
on some other SoCs as well, but those has not been tested
yet.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39149
2013-12-20 11:41:23 +00:00
Gabor Juhos
2c4e3cf33a ar71xx: ag71xx: get max_frame_len and desc_pktlen_mask from platform data
This will allow to use SoC specific values for both.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39145
2013-12-20 11:41:17 +00:00
Gabor Juhos
ba860e4c3a ar71xx: make ag71xx_mdio_platform_data visible
This enables us to modify the ag71xx_mdio_platform_data from within the
board support files.

Signed-off-by: Felix Kaechele <heffer@fedoraproject.org>
Patchwork: http://patchwork.openwrt.org/patch/4613/
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39126
2013-12-17 22:14:07 +00:00
Gabor Juhos
e312a917d3 ar71xx: rename ath79_parse_mac_addr to ath79_parse_ascii_mac
Rename the function and extend it in order to make it
usable from board setup code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 38085
2013-09-20 16:41:30 +00:00
Gabor Juhos
1d55249d7c ar71xx: use backported QCA955x patches
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 35878
2013-03-04 11:48:15 +00:00
Gabor Juhos
8a9d92f125 ar71xx: fix ethernet device registration for the QCA9556 SoC
Based on http://patchwork.openwrt.org/patch/3162/

Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 35394
2013-01-29 19:12:28 +00:00
Gabor Juhos
5dec87afef ar71xx: fix ethernet device registration for QCA9558
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34853
2012-12-22 12:12:48 +00:00
Gabor Juhos
4085a5773d ar71xx: fixup allowed PHY interface types for QCA9558
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34851
2012-12-22 12:12:44 +00:00
Gabor Juhos
f01a786825 ar71xx: don't assign any MII bus device on QCA9558 by default
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34850
2012-12-22 12:12:43 +00:00
Gabor Juhos
5ffc08e3dc ar71xx: add a helper function for setting up ETH_CFG register on AR934x
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33817
2012-10-17 18:27:45 +00:00
Gabor Juhos
170cd7a19a ar71xx: avoid possible NULL pointer dereference in ath79_init_{,local}_mac
SVN-Revision: 33575
2012-09-27 20:05:42 +00:00
Gabor Juhos
94bac7366c ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
SVN-Revision: 33343
2012-09-09 14:05:20 +00:00
Gabor Juhos
11c3392b7f Revert "ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240"
That was based on assumptions.

SVN-Revision: 33310
2012-08-29 10:37:55 +00:00
Gabor Juhos
cca873e8e0 ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240
Signed-off-by: Daniel Golle <dgolle@allnet.de>

SVN-Revision: 33280
2012-08-27 14:55:26 +00:00
Gabor Juhos
d1b237b335 ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
2012-07-05 08:26:47 +00:00
Felix Fietkau
dc9675282e ar71xx: add a helper function for setting up PHY4 swapping on ar933x
SVN-Revision: 32092
2012-06-06 17:24:09 +00:00
Felix Fietkau
8039a1bbb2 ar71xx: fix MII clock settings for various chips, improves ethernet stability on AR934x
SVN-Revision: 31925
2012-05-27 21:02:41 +00:00
Gabor Juhos
3e3a4d3d6b ar71xx: allow to disable link polling on unused PHYs
SVN-Revision: 31533
2012-04-29 18:29:24 +00:00
Gabor Juhos
e9b45ebaba ar71xx: add AR934x specific interface speed setup for ge0
SVN-Revision: 31017
2012-03-19 11:11:20 +00:00
Gabor Juhos
1c5ac02a29 ar71xx: reset the switch on AR934x before ethernet device registration
SVN-Revision: 30922
2012-03-13 17:29:33 +00:00
Gabor Juhos
66df117d1b ar71xx: use a dummy callback for interfaces with fixed speed
SVN-Revision: 30913
2012-03-12 20:38:58 +00:00
Gabor Juhos
8b2b37ae58 ar71xx: merge ar934x_bo_ddr_flush patch
SVN-Revision: 30912
2012-03-12 20:38:57 +00:00
Gabor Juhos
d72bde99cd ar71xx: merge files-3.2 to files
SVN-Revision: 30405
2012-02-10 08:19:31 +00:00
Renamed from target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.c (Browse further)