ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
SVN-Revision: 33343
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7592057774
commit
94bac7366c
2 changed files with 47 additions and 4 deletions
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@ -19,6 +19,7 @@
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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@ -146,6 +147,31 @@ static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
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iounmap(base);
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}
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static unsigned long ar934x_get_mdio_ref_clock(void)
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{
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void __iomem *base;
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unsigned long ret;
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u32 t;
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base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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ret = 0;
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t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
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ret = 100 * 1000 * 1000;
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} else {
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struct clk *clk;
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clk = clk_get(NULL, "ref");
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if (!IS_ERR(clk))
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ret = clk_get_rate(clk);
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}
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iounmap(base);
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return ret;
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}
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void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
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{
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struct platform_device *mdio_dev;
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@ -217,6 +243,13 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
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case ATH79_SOC_AR9341:
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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if (id == 1) {
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mdio_data->builtin_switch = 1;
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mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
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mdio_data->mdio_clock = 6250000;
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}
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mdio_data->is_ar934x = 1;
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break;
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case ATH79_SOC_QCA9558:
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if (id == 1)
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mdio_data->builtin_switch = 1;
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@ -74,15 +74,25 @@
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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@@ -212,6 +232,7 @@
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@@ -212,6 +232,8 @@
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#define AR934X_PLL_CPU_CONFIG_REG 0x00
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#define AR934X_PLL_DDR_CONFIG_REG 0x04
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
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+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -370,16 +391,50 @@
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@@ -244,6 +266,8 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
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+
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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@@ -370,16 +394,50 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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@ -133,7 +143,7 @@
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -520,6 +575,14 @@
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@@ -520,6 +578,14 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -148,7 +158,7 @@
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#define AR71XX_GPIO_COUNT 16
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#define AR724X_GPIO_COUNT 18
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#define AR913X_GPIO_COUNT 22
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@@ -548,4 +611,133 @@
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@@ -548,4 +614,133 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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