Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x"
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some boards. These boards depend on the preset values of u-boot which may differ. This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49071
This commit is contained in:
parent
26d18d4e07
commit
b269a3520d
17 changed files with 19 additions and 29 deletions
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@ -830,9 +830,7 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
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iounmap(base);
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}
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void __init ath79_setup_qca955x_eth_cfg(u32 mask,
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unsigned int rxd, unsigned int rxdv,
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unsigned int txd, unsigned int txe)
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void __init ath79_setup_qca955x_eth_cfg(u32 mask)
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{
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void __iomem *base;
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u32 t, m;
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@ -847,10 +845,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
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QCA955X_ETH_CFG_RMII_GE0 |
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QCA955X_ETH_CFG_MII_CNTL_SPEED |
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QCA955X_ETH_CFG_RMII_GE0_MASTER;
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m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
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m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
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m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
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m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
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base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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@ -858,10 +852,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
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t &= ~m;
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t |= mask;
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t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
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t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
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t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
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t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
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__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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@ -48,7 +48,6 @@ void ath79_register_mdio(unsigned int id, u32 phy_mask);
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void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
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void ath79_setup_ar934x_eth_cfg(u32 mask);
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void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
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void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
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unsigned int txd, unsigned int txe);
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void ath79_setup_qca955x_eth_cfg(u32 mask);
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#endif /* _ATH79_DEV_ETH_H */
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@ -211,7 +211,7 @@ static void __init common_setup(bool pcie_slot)
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ARRAY_SIZE(archer_c7_mdio0_info));
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ath79_register_mdio(0, 0x0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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@ -149,7 +149,7 @@ static void __init epg5000_setup(void)
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ath79_register_usb();
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -148,7 +148,7 @@ static void __init esr1750_setup(void)
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ath79_register_usb();
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -170,7 +170,7 @@ static void __init esr900_setup(void)
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ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -152,7 +152,7 @@ static void __init f9k1115v2_setup(void)
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mdiobus_register_board_info(f9k1115v2_mdio0_info,
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ARRAY_SIZE(f9k1115v2_mdio0_info));
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_init_mac(ath79_eth0_data.mac_addr,
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art + F9K1115V2_WAN_MAC_OFFSET, 0);
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@ -253,8 +253,9 @@ static void __init mr18_setup(void)
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res = mr18_extract_sgmii_res_cal();
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if (res >= 0) {
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/* Setup SoC Eth Config */
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0,
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0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN |
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(3 << QCA955X_ETH_CFG_RXD_DELAY_SHIFT) |
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(3 << QCA955X_ETH_CFG_RDV_DELAY_SHIFT));
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/* MDIO Interface */
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ath79_register_mdio(0, 0x0);
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@ -287,7 +287,7 @@ static void __init nbg6716_common_setup(u32 leds_num, struct gpio_led* leds,
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ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -203,7 +203,7 @@ static void __init rb922gs_setup(void)
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rb922gs_nand_init();
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -155,7 +155,7 @@ static void __init tew_823dru_setup(void)
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ARRAY_SIZE(tew_823dru_mdio0_info));
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ath79_register_mdio(0, 0x0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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@ -183,7 +183,7 @@ static void __init tl_wr1043nd_v2_setup(void)
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ARRAY_SIZE(wr1043nd_v2_mdio0_info));
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ath79_register_mdio(0, 0x0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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@ -152,7 +152,7 @@ static void __init wlr8100_common_setup(void)
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ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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@ -156,7 +156,7 @@ static void __init wpj558_setup(void)
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ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to an AR8327 switch */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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@ -193,7 +193,7 @@ static void __init wzr_450hp2_setup(void)
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ARRAY_SIZE(wzr_450hp2_mdio0_info));
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ath79_register_mdio(0, 0x0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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@ -149,7 +149,7 @@
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+
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+ ath79_register_mdio(0, 0x0);
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@ -149,7 +149,7 @@
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+
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+ ath79_register_mdio(0, 0x0);
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