22c5f96c6b
Some u-boot versions for QCA955x change the delays based on the link speed during boot. This usually breaks the support of other linkspeeds when OpenWrt is booted. It also conflicts with the at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own values in QCA955X_GMAC_REG_ETH_CFG. The default RGMII values from the Atheros u-boot are currently used to preset the existing mach files. These may have to be adjusted for boards using different values but which are not currently set them explicitely in OpenWrt. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Christian Beier <cb@shoutrlabs.com> Cc: Chris R Blake <chrisrblake93@gmail.com> Cc: Benjamin Berg <benjamin@sipsolutions.net> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com> Cc: Matthias Schiffer <mschiffer@universe-factory.net> Cc: Dirk Neukirchen <dirkneukirchen@web.de> Cc: Christian Mehlis <christian@m3hlis.de> Cc: Luka Perkov <luka@openwrt.org> Cc: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 49029
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/*
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* MR1750 board support
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*
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* Copyright (c) 2012 Qualcomm Atheros
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* Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "pci.h"
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#define MR1750_GPIO_LED_LAN 12
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#define MR1750_GPIO_LED_WLAN_2G 13
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#define MR1750_GPIO_LED_STATUS_GREEN 19
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#define MR1750_GPIO_LED_STATUS_RED 21
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#define MR1750_GPIO_LED_POWER 22
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#define MR1750_GPIO_LED_WLAN_5G 23
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#define MR1750_GPIO_BTN_RESET 17
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#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */
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#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL)
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#define MR1750_MAC0_OFFSET 0
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#define MR1750_WMAC_CALDATA_OFFSET 0x1000
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static struct gpio_led mr1750_leds_gpio[] __initdata = {
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{
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.name = "mr1750:blue:power",
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.gpio = MR1750_GPIO_LED_POWER,
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.active_low = 1,
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},
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{
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.name = "mr1750:blue:wan",
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.gpio = MR1750_GPIO_LED_LAN,
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.active_low = 1,
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},
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{
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.name = "mr1750:blue:wlan24",
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.gpio = MR1750_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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{
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.name = "mr1750:blue:wlan58",
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.gpio = MR1750_GPIO_LED_WLAN_5G,
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.active_low = 1,
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},
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{
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.name = "mr1750:green:status",
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.gpio = MR1750_GPIO_LED_STATUS_GREEN,
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.active_low = 1,
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},
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{
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.name = "mr1750:red:status",
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.gpio = MR1750_GPIO_LED_STATUS_RED,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button mr1750_gpio_keys[] __initdata = {
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL,
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.gpio = MR1750_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static void __init mr1750_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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ath79_eth0_pll_data.pll_1000 = 0xbe000101;
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ath79_eth0_pll_data.pll_100 = 0x80000101;
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ath79_eth0_pll_data.pll_10 = 0x80001313;
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio),
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mr1750_leds_gpio);
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ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(mr1750_gpio_keys),
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mr1750_gpio_keys);
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ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1);
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ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
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ath79_register_pci();
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(5);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup);
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