22c5f96c6b
Some u-boot versions for QCA955x change the delays based on the link speed during boot. This usually breaks the support of other linkspeeds when OpenWrt is booted. It also conflicts with the at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own values in QCA955X_GMAC_REG_ETH_CFG. The default RGMII values from the Atheros u-boot are currently used to preset the existing mach files. These may have to be adjusted for boards using different values but which are not currently set them explicitely in OpenWrt. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Christian Beier <cb@shoutrlabs.com> Cc: Chris R Blake <chrisrblake93@gmail.com> Cc: Benjamin Berg <benjamin@sipsolutions.net> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com> Cc: Matthias Schiffer <mschiffer@universe-factory.net> Cc: Dirk Neukirchen <dirkneukirchen@web.de> Cc: Christian Mehlis <christian@m3hlis.de> Cc: Luka Perkov <luka@openwrt.org> Cc: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 49029
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/*
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* Atheros AR71xx SoC device definitions
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*
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* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _ATH79_DEV_ETH_H
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#define _ATH79_DEV_ETH_H
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#include <asm/mach-ath79/ag71xx_platform.h>
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struct platform_device;
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extern unsigned char ath79_mac_base[] __initdata;
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void ath79_parse_ascii_mac(char *mac_str, u8 *mac);
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void ath79_init_mac(unsigned char *dst, const unsigned char *src,
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int offset);
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void ath79_init_local_mac(unsigned char *dst, const unsigned char *src);
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struct ath79_eth_pll_data {
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u32 pll_10;
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u32 pll_100;
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u32 pll_1000;
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};
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extern struct ath79_eth_pll_data ath79_eth0_pll_data;
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extern struct ath79_eth_pll_data ath79_eth1_pll_data;
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extern struct ag71xx_platform_data ath79_eth0_data;
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extern struct ag71xx_platform_data ath79_eth1_data;
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extern struct platform_device ath79_eth0_device;
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extern struct platform_device ath79_eth1_device;
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void ath79_register_eth(unsigned int id);
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extern struct ag71xx_switch_platform_data ath79_switch_data;
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extern struct ag71xx_mdio_platform_data ath79_mdio0_data;
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extern struct ag71xx_mdio_platform_data ath79_mdio1_data;
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extern struct platform_device ath79_mdio0_device;
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extern struct platform_device ath79_mdio1_device;
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void ath79_register_mdio(unsigned int id, u32 phy_mask);
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void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
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void ath79_setup_ar934x_eth_cfg(u32 mask);
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void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
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void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
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unsigned int txd, unsigned int txe);
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#endif /* _ATH79_DEV_ETH_H */
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