b1d57dadb2
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms" datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a 40 Mhz reference clock. The register description for "Bootstrap Options" (page 31) defines following states for the bit 4 (REF_CLK): * 0 - CLK25 (default) * 1 - (reserved) Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25 Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and then break the bootup of the system due to this incorrect interpretation. Signed-off-by: Sven Eckelmann <sven@narfation.org> [refreshed patches] Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
24 lines
701 B
Diff
24 lines
701 B
Diff
--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -406,6 +406,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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ar934x_set_ext_lna_gpio(chain, gpio);
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}
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+void __init ath79_wmac_set_led_pin(int gpio)
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+{
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+ ath79_wmac_data.led_pin = gpio;
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+}
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+
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void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
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{
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if (soc_is_ar913x())
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--- a/arch/mips/ath79/dev-wmac.h
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+++ b/arch/mips/ath79/dev-wmac.h
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@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void);
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void ath79_wmac_disable_5ghz(void);
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void ath79_wmac_set_tx_gain_buffalo(void);
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void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio);
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+void ath79_wmac_set_led_pin(int gpio);
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bool ar93xx_wmac_read_mac_address(u8 *dest);
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