ar71xx: disable 40Mhz refclk for QCA953x
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms" datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a 40 Mhz reference clock. The register description for "Bootstrap Options" (page 31) defines following states for the bit 4 (REF_CLK): * 0 - CLK25 (default) * 1 - (reserved) Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25 Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and then break the bootup of the system due to this incorrect interpretation. Signed-off-by: Sven Eckelmann <sven@narfation.org> [refreshed patches] Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
This commit is contained in:
Sven Eckelmann
Piotr Dymacz
parent
c6bd0b4894
commit
b1d57dadb2
8 changed files with 32 additions and 50 deletions
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@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -354,6 +354,91 @@ static void __init ar934x_clocks_init(vo
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@@ -354,6 +354,87 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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@ -56,13 +56,9 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+ /* QCA953X only supports 25MHz ref_clk */
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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@ -136,7 +132,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@@ -451,6 +536,8 @@ void __init ath79_clocks_init(void)
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@@ -451,6 +532,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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@ -247,14 +243,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
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}
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@@ -150,6 +150,26 @@ static void ar934x_wmac_setup(void)
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@@ -150,6 +150,21 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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+static void qca953x_wmac_setup(void)
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+{
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+ u32 t;
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+
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+ ath79_wmac_device.name = "qca953x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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@ -262,11 +256,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
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+
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+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+ /* QCA953X only supports 25MHz ref_clk */
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+ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+}
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@ -274,7 +265,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -379,6 +399,8 @@ void __init ath79_register_wmac(u8 *cal_
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@@ -379,6 +394,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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@ -550,7 +541,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
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+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
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+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
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+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
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+#define QCA953X_BOOTSTRAP_REF_CLK BIT(4)
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+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
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+
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@ -24,7 +24,7 @@
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v
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@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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@ -125,7 +125,7 @@
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -540,6 +634,8 @@ void __init ath79_clocks_init(void)
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@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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@ -219,7 +219,7 @@
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}
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -200,6 +200,26 @@ static void qca955x_wmac_setup(void)
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@@ -195,6 +195,26 @@ static void qca955x_wmac_setup(void)
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#define AR93XX_OTP_READ_DATA \
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(soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
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@ -246,7 +246,7 @@
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static bool __init
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ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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{
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@@ -403,6 +423,8 @@ void __init ath79_register_wmac(u8 *cal_
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@@ -398,6 +418,8 @@ void __init ath79_register_wmac(u8 *cal_
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qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -411,6 +411,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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@@ -406,6 +406,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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ar934x_set_ext_lna_gpio(chain, gpio);
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}
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@ -32,7 +32,7 @@
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*/
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -170,6 +170,27 @@ static void qca953x_wmac_setup(void)
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@@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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@ -60,7 +60,7 @@
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -186,6 +207,8 @@ static void qca955x_wmac_setup(void)
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@@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -358,6 +358,91 @@ static void __init ar934x_clocks_init(vo
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@@ -358,6 +358,87 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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@ -56,13 +56,9 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+ /* QCA953X only supports 25MHz ref_clk */
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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@ -136,7 +132,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@@ -453,6 +538,8 @@ void __init ath79_clocks_init(void)
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@@ -453,6 +534,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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@ -247,14 +243,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
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}
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@@ -150,6 +150,26 @@ static void ar934x_wmac_setup(void)
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@@ -150,6 +150,21 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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+static void qca953x_wmac_setup(void)
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+{
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+ u32 t;
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+
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+ ath79_wmac_device.name = "qca953x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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@ -262,11 +256,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
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+
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+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+ /* QCA953X only supports 25MHz ref_clk */
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+ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+}
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@ -274,7 +265,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -379,6 +399,8 @@ void __init ath79_register_wmac(u8 *cal_
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@@ -379,6 +394,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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@ -550,7 +541,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
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+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
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+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
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+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
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+#define QCA953X_BOOTSTRAP_REF_CLK BIT(4)
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+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
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+
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@ -24,7 +24,7 @@
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -528,6 +528,100 @@ static void __init qca955x_clocks_init(v
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@@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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@ -125,7 +125,7 @@
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -542,6 +636,8 @@ void __init ath79_clocks_init(void)
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@@ -538,6 +632,8 @@ void __init ath79_clocks_init(void)
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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@ -219,7 +219,7 @@
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}
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -200,6 +200,26 @@ static void qca955x_wmac_setup(void)
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@@ -195,6 +195,26 @@ static void qca955x_wmac_setup(void)
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#define AR93XX_OTP_READ_DATA \
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(soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
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@ -246,7 +246,7 @@
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static bool __init
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ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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{
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@@ -403,6 +423,8 @@ void __init ath79_register_wmac(u8 *cal_
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@@ -398,6 +418,8 @@ void __init ath79_register_wmac(u8 *cal_
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qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -411,6 +411,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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@@ -406,6 +406,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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ar934x_set_ext_lna_gpio(chain, gpio);
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}
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@ -32,7 +32,7 @@
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*/
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -170,6 +170,27 @@ static void qca953x_wmac_setup(void)
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@@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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@ -60,7 +60,7 @@
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -186,6 +207,8 @@ static void qca955x_wmac_setup(void)
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@@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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