cf039cf7ff
This adds the device tree changes needed to make the GMAC stmmac driver working for the Allwinner A64 SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
69 lines
2.1 KiB
Diff
69 lines
2.1 KiB
Diff
From e53f67e981bcc5547857475241b3a4a066955f8c Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:46 +0200
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Subject: arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
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The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
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connections. It is very similar to the device found in the Allwinner
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H3, but lacks the internal 100 Mbit PHY and its associated control
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bits.
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This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
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it disabled at this level.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 +++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -284,6 +284,21 @@
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bias-pull-up;
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};
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+ rmii_pins: rmii_pins {
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+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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+ "PD18", "PD19", "PD20", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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+ rgmii_pins: rgmii_pins {
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+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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+ "PD13", "PD15", "PD16", "PD17", "PD18",
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+ "PD19", "PD20", "PD21", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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@@ -388,6 +403,26 @@
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#size-cells = <0>;
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};
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+ emac: ethernet@1c30000 {
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+ compatible = "allwinner,sun50i-a64-emac";
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+ syscon = <&syscon>;
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+ reg = <0x01c30000 0x100>;
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+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mdio: mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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