sunxi: A64: add device tree changes for A64 Ethernet
This adds the device tree changes needed to make the GMAC stmmac driver working for the Allwinner A64 SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens
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cf039cf7ff
6 changed files with 241 additions and 0 deletions
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From 79b953605ded6a9a995040a1c8cc665127a6411a Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:45 +0200
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Subject: arm64: allwinner: sun50i-a64: Add dt node for the syscon control
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module
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This patch add the dt node for the syscon register present on the
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Allwinner A64.
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Only two register are present in this syscon and the only one useful is
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the one dedicated to EMAC clock.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -129,6 +129,12 @@
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#size-cells = <1>;
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ranges;
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+ syscon: syscon@1c00000 {
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+ compatible = "allwinner,sun50i-a64-system-controller",
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+ "syscon";
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+ reg = <0x01c00000 0x1000>;
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+ };
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+
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -0,0 +1,69 @@
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From e53f67e981bcc5547857475241b3a4a066955f8c Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:46 +0200
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Subject: arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
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The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
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connections. It is very similar to the device found in the Allwinner
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H3, but lacks the internal 100 Mbit PHY and its associated control
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bits.
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This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
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it disabled at this level.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 +++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -284,6 +284,21 @@
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bias-pull-up;
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};
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+ rmii_pins: rmii_pins {
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+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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+ "PD18", "PD19", "PD20", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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+ rgmii_pins: rgmii_pins {
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+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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+ "PD13", "PD15", "PD16", "PD17", "PD18",
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+ "PD19", "PD20", "PD21", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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@@ -388,6 +403,26 @@
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#size-cells = <0>;
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};
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+ emac: ethernet@1c30000 {
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+ compatible = "allwinner,sun50i-a64-emac";
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+ syscon = <&syscon>;
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+ reg = <0x01c30000 0x100>;
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+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mdio: mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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@ -0,0 +1,46 @@
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From 97023943749367111b9a88e09d1b9bd157dd3326 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:47 +0200
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Subject: arm64: allwinner: pine64: Enable dwmac-sun8i
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The dwmac-sun8i hardware is present on the pine64
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It uses an external PHY via RMII.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -70,6 +70,15 @@
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status = "okay";
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&rmii_pins>;
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+ phy-mode = "rmii";
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+ phy-handle = <&ext_rmii_phy1>;
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+ status = "okay";
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+
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+};
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+
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -80,6 +89,13 @@
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bias-pull-up;
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};
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+&mdio {
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+ ext_rmii_phy1: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@ -0,0 +1,38 @@
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From 94dcfdc77fc55ed1956011ceea341911c6e760a0 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:48 +0200
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Subject: arm64: allwinner: pine64-plus: Enable dwmac-sun8i
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The dwmac-sun8i hardware is present on the pine64 plus.
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It uses an external PHY rtl8211e via RGMII.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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.../arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 17 ++++++++++++++++-
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1 file changed, 16 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
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@@ -46,5 +46,20 @@
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model = "Pine64+";
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compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
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- /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
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+ /* TODO: Camera, touchscreen, etc. */
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+};
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+
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&rgmii_pins>;
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+ phy-mode = "rgmii";
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+ phy-handle = <&ext_rgmii_phy>;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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};
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@ -0,0 +1,26 @@
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From 3a4bae5fd44aa1cf49780dd25b3a89e6a39e8560 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Mon, 10 Jul 2017 20:44:40 +0200
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Subject: arm64: allwinner: sun50i-a64: Correct emac register size
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The datasheet said that emac register size is 0x10000 not 0x100
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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[wens@csie.org: Fixed commit subject prefix]
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -406,7 +406,7 @@
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun50i-a64-emac";
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syscon = <&syscon>;
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- reg = <0x01c30000 0x100>;
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+ reg = <0x01c30000 0x10000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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@ -0,0 +1,29 @@
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From dff751c68904cf587d918cfb6b2f5b0112f73bc9 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sat, 22 Jul 2017 10:28:51 +0800
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Subject: arm64: allwinner: a64: pine64: add missing ethernet0 alias
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The EMAC Ethernet controller was enabled, but an accompanying alias
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was not added. This results in unstable numbering if other Ethernet
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devices, such as a USB dongle, are present. Also, the bootloader uses
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the alias to assign a generated stable MAC address to the device node.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Fixes: 970239437493 ("arm64: allwinner: pine64: Enable dwmac-sun8i")
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[wens@csie.org: Rewrite commit log as fixing a previous patch with Fixes]
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
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@@ -51,6 +51,7 @@
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compatible = "pine64,pine64", "allwinner,sun50i-a64";
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aliases {
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+ ethernet0 = &emac;
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serial0 = &uart0;
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};
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