799d0dddf6
The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
38 lines
1.1 KiB
Diff
38 lines
1.1 KiB
Diff
From 2f3ea65dc8909cbf4116bd74b3dea8d25749508f Mon Sep 17 00:00:00 2001
|
|
From: Zhao Qiang <qiang.zhao@nxp.com>
|
|
Date: Wed, 23 Nov 2016 11:29:45 +0800
|
|
Subject: [PATCH 235/238] pci/layerscape: fix pci lut offset issue
|
|
|
|
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
---
|
|
drivers/pci/host/pci-layerscape.c | 13 ++++---------
|
|
1 file changed, 4 insertions(+), 9 deletions(-)
|
|
|
|
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
|
|
index f85ebcf..00feabf 100644
|
|
--- a/drivers/pci/host/pci-layerscape.c
|
|
+++ b/drivers/pci/host/pci-layerscape.c
|
|
@@ -158,16 +158,11 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
|
|
static int ls_pcie_link_up(struct pcie_port *pp)
|
|
{
|
|
struct ls_pcie *pcie = to_ls_pcie(pp);
|
|
- u32 state, offset;
|
|
-
|
|
- if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL))
|
|
- offset = 0x407fc;
|
|
- else
|
|
- offset = PCIE_LUT_DBG;
|
|
+ u32 state;
|
|
|
|
- state = (ioread32(pcie->lut + offset) >>
|
|
- pcie->drvdata->ltssm_shift) &
|
|
- LTSSM_STATE_MASK;
|
|
+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
|
|
+ pcie->drvdata->ltssm_shift) &
|
|
+ LTSSM_STATE_MASK;
|
|
|
|
if (state < LTSSM_PCIE_L0)
|
|
return 0;
|
|
--
|
|
1.7.9.5
|
|
|