3dd692cd6b
95672e04 broke booting secondary cores by removing 'qcom,saw' property
from L2 cache node. kpssv2_release_secondary() requires it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
85 lines
2 KiB
Diff
85 lines
2 KiB
Diff
From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Mon, 23 Jul 2018 09:10:35 +0200
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Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
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support
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This adds some operating points for cpu frequeny scaling
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
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1 file changed, 26 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -41,14 +41,7 @@
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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- clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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@@ -61,6 +54,7 @@
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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@@ -73,6 +67,7 @@
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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@@ -85,6 +80,7 @@
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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L2: l2-cache {
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@@ -94,6 +90,28 @@
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};
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};
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+ cpu0_opp_table: opp_table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-48000000 {
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+ opp-hz = /bits/ 64 <48000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-716000000 {
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+ opp-hz = /bits/ 64 <716000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ };
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+
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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