openwrtv4/target/linux/lantiq/dts/vr9.dtsi
Felix Fietkau 3f8a426056 lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	pcie_rc_initialize link up failed!!!!!

To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48285
2016-01-17 19:55:10 +00:00

198 lines
4.1 KiB
Text

/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,xway", "lantiq,vr9";
cpus {
cpu@0 {
compatible = "mips,mips34Kc";
};
};
memory@0 {
device_type = "memory";
};
biu@1F800000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,biu", "simple-bus";
reg = <0x1F800000 0x800000>;
ranges = <0x0 0x1F800000 0x7FFFFF>;
icu0: icu@80200 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,icu";
reg = <0x80200 0x28
0x80228 0x28
0x80250 0x28
0x80278 0x28
0x802a0 0x28>;
};
watchdog@803F0 {
compatible = "lantiq,wdt";
reg = <0x803F0 0x10>;
};
};
sram@1F000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,sram", "simple-bus";
reg = <0x1F000000 0x800000>;
ranges = <0x0 0x1F000000 0x7FFFFF>;
eiu0: eiu@101000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,eiu-xway";
reg = <0x101000 0x1000>;
interrupt-parent = <&icu0>;
interrupts = <166 135 66 40 41 42>;
};
pmu0: pmu@102000 {
compatible = "lantiq,pmu-xway";
reg = <0x102000 0x1000>;
};
cgu0: cgu@103000 {
compatible = "lantiq,cgu-xway";
reg = <0x103000 0x1000>;
};
dcdc@106a00 {
compatible = "lantiq,dcdc-xrx200";
reg = <0x106a00 0x200>;
};
rcu0: rcu@203000 {
compatible = "lantiq,rcu-xrx200";
reg = <0x203000 0x1000>;
/* irq for thermal sensor */
interrupt-parent = <&icu0>;
interrupts = <115>;
};
xbar0: xbar@400000 {
compatible = "lantiq,xbar-xway";
reg = <0x400000 0x1000>;
};
};
fpi@10000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,fpi", "simple-bus";
ranges = <0x0 0x10000000 0xEEFFFFF>;
reg = <0x10000000 0xEF00000>;
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
1 0 0x4000000 0x4000010>; /* addsel1 */
compatible = "lantiq,localbus", "simple-bus";
};
gptu@E100A00 {
compatible = "lantiq,gptu-xway";
reg = <0xE100A00 0x100>;
interrupt-parent = <&icu0>;
interrupts = <126 127 128 129 130 131>;
};
asc0: serial@E100400 {
compatible = "lantiq,asc";
reg = <0xE100400 0x400>;
interrupt-parent = <&icu0>;
interrupts = <104 105 106>;
status = "disabled";
};
gpio: pinmux@E100B10 {
compatible = "lantiq,xrx200-pinctrl";
#gpio-cells = <2>;
gpio-controller;
reg = <0xE100B10 0xA0>;
};
asc1: serial@E100C00 {
compatible = "lantiq,asc";
reg = <0xE100C00 0x400>;
interrupt-parent = <&icu0>;
interrupts = <112 113 114>;
};
deu@E103100 {
compatible = "lantiq,deu-xrx200";
reg = <0xE103100 0xf00>;
};
dma0: dma@E104100 {
compatible = "lantiq,dma-xway";
reg = <0xE104100 0x800>;
};
ebu0: ebu@E105300 {
compatible = "lantiq,ebu-xway";
reg = <0xE105300 0x100>;
};
ifxhcd@E101000 {
status = "disabled";
compatible = "lantiq,ifxhcd-xrx200", "lantiq,ifxhcd-xrx200-dwc2";
reg = <0xE101000 0x1000
0xE120000 0x3f000>;
interrupt-parent = <&icu0>;
interrupts = <62 91>;
};
ifxhcd@E106000 {
status = "disabled";
compatible = "lantiq,ifxhcd-xrx200-dwc2";
reg = <0xE106000 0x1000>;
interrupt-parent = <&icu0>;
interrupts = <91>;
};
mei@E116000 {
compatible = "lantiq,mei-xrx200";
reg = <0xE116000 0x9c>;
interrupt-parent = <&icu0>;
interrupts = <63>;
};
ppe@E234000 {
compatible = "lantiq,ppe-xrx200";
interrupt-parent = <&icu0>;
interrupts = <96>;
};
pcie@d900000 {
interrupt-parent = <&icu0>;
interrupts = <161 144>;
compatible = "lantiq,pcie-xrx200";
gpio-reset = <&gpio 38 0>;
};
pci0: pci@E105400 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "lantiq,pci-xway";
bus-range = <0x0 0x0>;
ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
reg = <0x7000000 0x8000 /* config space */
0xE105400 0x400>; /* pci bridge */
status = "disabled";
};
};
vdsl {
compatible = "lantiq,vdsl-vrx200";
};
};