Felix Fietkau 3f8a426056 lantiq: Configure the PCIe reset GPIO using OF ... After the latest pinctrl backports there are only 50 (instead of 56 as before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now 462, before it was 456). This means that any hardcoded GPIOs have to be adjusted. This broke the PCIe driver (which seems to be the only driver which uses hardcoded GPIO numbers), it only reports: ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout pcie_rc_initialize link up failed!!!!! To prevent more of these issues in the future we remove the hardcoded PCIe reset GPIO definition and simply pass it via device-tree (like the PCI driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48285		2016-01-17 19:55:10 +00:00
..
imagebuilder	images imagebuilder: Allow to add sanitized extra name	2016-01-03 14:44:56 +00:00
linux	lantiq: Configure the PCIe reset GPIO using OF	2016-01-17 19:55:10 +00:00
sdk	sdk: add base repository fallback	2016-01-12 09:25:45 +00:00
toolchain	targets: Use configured distribution name for SDK, IB, and Toolchain tarball names	2016-01-03 14:44:42 +00:00
Config.in	toolchain: add support of ARC architecture	2015-11-10 12:03:59 +00:00
Makefile