db36359f48
Remove the non runtime detect code since its effectiveness is dubious and almost never used. Also update affinity patches to work on top of it. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39268
158 lines
4.6 KiB
Diff
158 lines
4.6 KiB
Diff
From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 21 Apr 2013 15:38:56 +0200
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Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
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---
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arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -12,6 +12,7 @@
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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+#include <linux/spinlock.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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@@ -20,6 +21,9 @@
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#include <bcm63xx_irq.h>
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+static DEFINE_SPINLOCK(ipic_lock);
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+static DEFINE_SPINLOCK(epic_lock);
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+
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static u32 irq_stat_addr[2];
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static u32 irq_mask_addr[2];
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static void (*dispatch_internal)(int pin);
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@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin
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bool irqs_pending = false; \
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static int i[2]; \
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int *next = &i[pin]; \
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+ unsigned long flags; \
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\
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/* read registers in reverse order */ \
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+ spin_lock_irqsave(&ipic_lock, flags); \
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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\
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@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin
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if (val) \
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irqs_pending = true; \
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} \
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+ spin_unlock_irqrestore(&ipic_lock, flags); \
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\
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if (!irqs_pending) \
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return; \
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@@ -94,10 +101,13 @@ static void __internal_irq_mask_##width(
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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+ unsigned long flags; \
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\
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+ spin_lock_irqsave(&ipic_lock, flags); \
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val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val &= ~(1 << bit); \
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bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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+ spin_unlock_irqrestore(&ipic_lock, flags); \
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} \
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\
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static void __internal_irq_unmask_##width(unsigned int irq) \
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@@ -105,10 +115,13 @@ static void __internal_irq_unmask_##widt
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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+ unsigned long flags; \
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\
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+ spin_lock_irqsave(&ipic_lock, flags); \
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val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val |= (1 << bit); \
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bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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+ spin_unlock_irqrestore(&ipic_lock, flags); \
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}
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BUILD_IPIC_INTERNAL(32);
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@@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(st
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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regaddr = get_ext_irq_perf_reg(irq);
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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@@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(st
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reg &= ~EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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+
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if (is_ext_irq_cascaded)
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internal_irq_mask(irq + ext_irq_start);
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}
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@@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask(
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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regaddr = get_ext_irq_perf_reg(irq);
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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@@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask(
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reg |= EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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if (is_ext_irq_cascaded)
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internal_irq_unmask(irq + ext_irq_start);
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@@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(s
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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regaddr = get_ext_irq_perf_reg(irq);
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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@@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(s
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reg |= EXTIRQ_CFG_CLEAR(irq % 4);
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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}
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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@@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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int levelsense, sense, bothedge;
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+ unsigned long flags;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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@@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type
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}
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regaddr = get_ext_irq_perf_reg(irq);
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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irq %= 4;
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@@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type
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}
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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