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brcm63xx: remove non runtime detect and refresh affinity patches

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Remove the non runtime detect code since its effectiveness is dubious
and almost never used.
Also update affinity patches to work on top of it.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 39268
This commit is contained in:
Jonas Gorski 2014-01-13 12:13:15 +00:00
parent d8ac24b325
commit db36359f48
24 changed files with 1368 additions and 752 deletions
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61
target/linux/brcm63xx/patches-3.10/310-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-registe.patch Normal file
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@ -0,0 +1,61 @@
From 082a49f0490008b999db80e3ccf1521c7dd21cec Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Mon, 2 Dec 2013 12:32:44 +0100
Subject: [PATCH 1/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code from register
sets
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 33 ------------------------
1 file changed, 33 deletions(-)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -598,10 +598,6 @@ enum bcm63xx_regs_set {
extern const unsigned long *bcm63xx_regs_base;
-#define __GEN_RSET_BASE(__cpu, __rset) \
- case RSET_## __rset : \
- return BCM_## __cpu ##_## __rset ##_BASE;
-
#define __GEN_RSET(__cpu) \
switch (set) { \
__GEN_RSET_BASE(__cpu, DSL_LMEM) \
@@ -693,36 +689,7 @@ extern const unsigned long *bcm63xx_regs
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
{
-#ifdef BCMCPU_RUNTIME_DETECT
return bcm63xx_regs_base[set];
-#else
-#ifdef CONFIG_BCM63XX_CPU_3368
- __GEN_RSET(3368)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6328
- __GEN_RSET(6328)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6338
- __GEN_RSET(6338)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6345
- __GEN_RSET(6345)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6348
- __GEN_RSET(6348)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6358
- __GEN_RSET(6358)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6362
- __GEN_RSET(6362)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
- __GEN_RSET(6368)
-#endif
-#endif
- /* unreached */
- return 0;
}
/*

135
target/linux/brcm63xx/patches-3.10/311-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-irq-setup-co.patch Normal file
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@ -0,0 +1,135 @@
From 07d0224576cbb2e6ac680b4ade4bba7a49bd0a07 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Mon, 2 Dec 2013 12:34:11 +0100
Subject: [PATCH 2/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from irq setup code
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 109 ------------------------------------------------
1 file changed, 109 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -26,114 +26,6 @@ static void __internal_irq_mask_64(unsig
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-#ifndef BCMCPU_RUNTIME_DETECT
-#ifdef CONFIG_BCM63XX_CPU_3368
-#define irq_stat_reg PERF_IRQSTAT_3368_REG
-#define irq_mask_reg PERF_IRQMASK_3368_REG
-#define irq_bits 32
-#define is_ext_irq_cascaded 0
-#define ext_irq_start 0
-#define ext_irq_end 0
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6328
-#define irq_stat_reg PERF_IRQSTAT_6328_REG
-#define irq_mask_reg PERF_IRQMASK_6328_REG
-#define irq_bits 64
-#define is_ext_irq_cascaded 1
-#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6338
-#define irq_stat_reg PERF_IRQSTAT_6338_REG
-#define irq_mask_reg PERF_IRQMASK_6338_REG
-#define irq_bits 32
-#define is_ext_irq_cascaded 0
-#define ext_irq_start 0
-#define ext_irq_end 0
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6345
-#define irq_stat_reg PERF_IRQSTAT_6345_REG
-#define irq_mask_reg PERF_IRQMASK_6345_REG
-#define irq_bits 32
-#define is_ext_irq_cascaded 0
-#define ext_irq_start 0
-#define ext_irq_end 0
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6348
-#define irq_stat_reg PERF_IRQSTAT_6348_REG
-#define irq_mask_reg PERF_IRQMASK_6348_REG
-#define irq_bits 32
-#define is_ext_irq_cascaded 0
-#define ext_irq_start 0
-#define ext_irq_end 0
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6358
-#define irq_stat_reg PERF_IRQSTAT_6358_REG
-#define irq_mask_reg PERF_IRQMASK_6358_REG
-#define irq_bits 32
-#define is_ext_irq_cascaded 1
-#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6362
-#define irq_stat_reg PERF_IRQSTAT_6362_REG
-#define irq_mask_reg PERF_IRQMASK_6362_REG
-#define irq_bits 64
-#define is_ext_irq_cascaded 1
-#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count 4
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362
-#define ext_irq_cfg_reg2 0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-#define irq_stat_reg PERF_IRQSTAT_6368_REG
-#define irq_mask_reg PERF_IRQMASK_6368_REG
-#define irq_bits 64
-#define is_ext_irq_cascaded 1
-#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
-#define ext_irq_count 6
-#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
-#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
-#endif
-
-#if irq_bits == 32
-#define dispatch_internal __dispatch_internal
-#define internal_irq_mask __internal_irq_mask_32
-#define internal_irq_unmask __internal_irq_unmask_32
-#else
-#define dispatch_internal __dispatch_internal_64
-#define internal_irq_mask __internal_irq_mask_64
-#define internal_irq_unmask __internal_irq_unmask_64
-#endif
-
-#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
-#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
-
-static inline void bcm63xx_init_irq(void)
-{
-}
-#else /* ! BCMCPU_RUNTIME_DETECT */
-
static u32 irq_stat_addr, irq_mask_addr;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
@@ -234,7 +126,6 @@ static void bcm63xx_init_irq(void)
internal_irq_unmask = __internal_irq_unmask_64;
}
}
-#endif /* ! BCMCPU_RUNTIME_DETECT */
static inline u32 get_ext_irq_perf_reg(int irq)
{

85
target/linux/brcm63xx/patches-3.10/312-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-reset-code.patch Normal file
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@ -0,0 +1,85 @@
From 72578a46543821c5b9544842e45fcbed0c1b7eb8 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Dec 2013 13:35:12 +0100
Subject: [PATCH 3/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from reset code
---
arch/mips/bcm63xx/reset.c | 60 -----------------------------------------------
1 file changed, 60 deletions(-)
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -125,8 +125,6 @@
#define BCM6368_RESET_PCIE 0
#define BCM6368_RESET_PCIE_EXT 0
-#ifdef BCMCPU_RUNTIME_DETECT
-
/*
* core reset bits
*/
@@ -188,64 +186,6 @@ static int __init bcm63xx_reset_bits_ini
return 0;
}
-#else
-
-#ifdef CONFIG_BCM63XX_CPU_3368
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(3368)
-};
-#define reset_reg PERF_SOFTRESET_6358_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6328
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6328)
-};
-#define reset_reg PERF_SOFTRESET_6328_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6338
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6338)
-};
-#define reset_reg PERF_SOFTRESET_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6345
-static const u32 bcm63xx_reset_bits[] = { };
-#define reset_reg 0
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6348
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6348)
-};
-#define reset_reg PERF_SOFTRESET_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6358
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6358)
-};
-#define reset_reg PERF_SOFTRESET_6358_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6362
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6362)
-};
-#define reset_reg PERF_SOFTRESET_6362_REG
-#endif
-
-#ifdef CONFIG_BCM63XX_CPU_6368
-static const u32 bcm63xx_reset_bits[] = {
- __GEN_RESET_BITS_TABLE(6368)
-};
-#define reset_reg PERF_SOFTRESET_6368_REG
-#endif
-
-static int __init bcm63xx_reset_bits_init(void) { return 0; }
-#endif
static DEFINE_SPINLOCK(reset_mutex);

39
target/linux/brcm63xx/patches-3.10/313-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-from-gpio.patch Normal file
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@ -0,0 +1,39 @@
From 1aab93c5c97c55fef130726a6f58c9a1fd5b6240 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Dec 2013 13:36:45 +0100
Subject: [PATCH 4/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code from gpio
---
arch/mips/bcm63xx/gpio.c | 14 --------------
1 file changed, 14 deletions(-)
--- a/arch/mips/bcm63xx/gpio.c
+++ b/arch/mips/bcm63xx/gpio.c
@@ -18,19 +18,6 @@
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
-#ifndef BCMCPU_RUNTIME_DETECT
-#define gpio_out_low_reg GPIO_DATA_LO_REG
-#ifdef CONFIG_BCM63XX_CPU_6345
-#ifdef gpio_out_low_reg
-#undef gpio_out_low_reg
-#define gpio_out_low_reg GPIO_DATA_LO_REG_6345
-#endif /* gpio_out_low_reg */
-#endif /* CONFIG_BCM63XX_CPU_6345 */
-
-static inline void bcm63xx_gpio_out_low_reg_init(void)
-{
-}
-#else /* ! BCMCPU_RUNTIME_DETECT */
static u32 gpio_out_low_reg;
static void bcm63xx_gpio_out_low_reg_init(void)
@@ -44,7 +31,6 @@ static void bcm63xx_gpio_out_low_reg_ini
break;
}
}
-#endif /* ! BCMCPU_RUNTIME_DETECT */
static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
static u32 gpio_out_low, gpio_out_high;

80
target/linux/brcm63xx/patches-3.10/314-MIPS-BCM63XX-remove-RUNTIME_DETECT-from-spi-code.patch Normal file
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@ -0,0 +1,80 @@
From 94f819bc230bb61a9ff21da6c860a40ca68c2805 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Dec 2013 13:43:35 +0100
Subject: [PATCH 5/8] MIPS: BCM63XX: remove !RUNTIME_DETECT from spi code
---
arch/mips/bcm63xx/dev-spi.c | 4 ---
.../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 31 ----------------------
2 files changed, 35 deletions(-)
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -18,7 +18,6 @@
#include <bcm63xx_dev_spi.h>
#include <bcm63xx_regs.h>
-#ifdef BCMCPU_RUNTIME_DETECT
/*
* register offsets
*/
@@ -41,9 +40,6 @@ static __init void bcm63xx_spi_regs_init
BCMCPU_IS_6362() || BCMCPU_IS_6368())
bcm63xx_regs_spi = bcm6358_regs_spi;
}
-#else
-static __init void bcm63xx_spi_regs_init(void) { }
-#endif
static struct resource spi_resources[] = {
{
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -30,26 +30,6 @@ enum bcm63xx_regs_spi {
SPI_RX_DATA,
};
-#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
- case SPI_## __rset: \
- return SPI_## __cpu ##_## __rset;
-
-#define __GEN_SPI_RSET(__cpu) \
- switch (reg) { \
- __GEN_SPI_RSET_BASE(__cpu, CMD) \
- __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
- __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
- __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
- __GEN_SPI_RSET_BASE(__cpu, ST) \
- __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
- __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
- __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
- __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
- __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
- __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
- __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
- }
-
#define __GEN_SPI_REGS_TABLE(__cpu) \
[SPI_CMD] = SPI_## __cpu ##_CMD, \
[SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
@@ -66,20 +46,9 @@ enum bcm63xx_regs_spi {
static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
{
-#ifdef BCMCPU_RUNTIME_DETECT
extern const unsigned long *bcm63xx_regs_spi;
return bcm63xx_regs_spi[reg];
-#else
-#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
- __GEN_SPI_RSET(6348)
-#endif
-#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
- defined(CONFIG_BCM63XX_CPU_6368)
- __GEN_SPI_RSET(6358)
-#endif
-#endif
- return 0;
}
#endif /* BCM63XX_DEV_SPI_H */

279
target/linux/brcm63xx/patches-3.10/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch
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@ -1,279 +0,0 @@
From 46442450ffb95a869894b0dfd1e5b4f973d4b4ee Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:24:06 +0200
Subject: [PATCH 07/14] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
The SMP capable irq controllers have two interupt output pins which are
controlled through separate registers.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 86 ++++++++++-----------
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++--
2 files changed, 51 insertions(+), 51 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
#ifndef BCMCPU_RUNTIME_DETECT
#ifdef CONFIG_BCM63XX_CPU_3368
-#define irq_stat_reg PERF_IRQSTAT_3368_REG
-#define irq_mask_reg PERF_IRQMASK_3368_REG
+#define irq_stat_reg0 PERF_IRQSTAT_3368_REG
+#define irq_mask_reg0 PERF_IRQMASK_3368_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
-#define irq_stat_reg PERF_IRQSTAT_6328_REG
-#define irq_mask_reg PERF_IRQMASK_6328_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
+#define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6338
-#define irq_stat_reg PERF_IRQSTAT_6338_REG
-#define irq_mask_reg PERF_IRQMASK_6338_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6338_REG
+#define irq_mask_reg0 PERF_IRQMASK_6338_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
-#define irq_stat_reg PERF_IRQSTAT_6345_REG
-#define irq_mask_reg PERF_IRQMASK_6345_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6345_REG
+#define irq_mask_reg0 PERF_IRQMASK_6345_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
-#define irq_stat_reg PERF_IRQSTAT_6348_REG
-#define irq_mask_reg PERF_IRQMASK_6348_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6348_REG
+#define irq_mask_reg0 PERF_IRQMASK_6348_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
-#define irq_stat_reg PERF_IRQSTAT_6358_REG
-#define irq_mask_reg PERF_IRQMASK_6358_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
+#define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
#define irq_bits 32
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6362
-#define irq_stat_reg PERF_IRQSTAT_6362_REG
-#define irq_mask_reg PERF_IRQMASK_6362_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
+#define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -105,8 +105,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
-#define irq_stat_reg PERF_IRQSTAT_6368_REG
-#define irq_mask_reg PERF_IRQMASK_6368_REG
+#define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
+#define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -126,15 +126,15 @@ static void __internal_irq_unmask_64(uns
#define internal_irq_unmask __internal_irq_unmask_64
#endif
-#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
-#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
+#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
+#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
static inline void bcm63xx_init_irq(void)
{
}
#else /* ! BCMCPU_RUNTIME_DETECT */
-static u32 irq_stat_addr, irq_mask_addr;
+static u32 irq_stat_addr0, irq_mask_addr0;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
@@ -147,20 +147,20 @@ static void bcm63xx_init_irq(void)
{
int irq_bits;
- irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+ irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_3368_REG;
- irq_mask_addr += PERF_IRQMASK_3368_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
+ irq_mask_addr0 += PERF_IRQMASK_3368_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
break;
case BCM6328_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6328_REG;
- irq_mask_addr += PERF_IRQMASK_6328_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
+ irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -169,29 +169,29 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
break;
case BCM6338_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6338_REG;
- irq_mask_addr += PERF_IRQMASK_6338_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6338_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
break;
case BCM6345_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6345_REG;
- irq_mask_addr += PERF_IRQMASK_6345_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6345_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
break;
case BCM6348_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6348_REG;
- irq_mask_addr += PERF_IRQMASK_6348_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6348_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
break;
case BCM6358_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6358_REG;
- irq_mask_addr += PERF_IRQMASK_6358_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
+ irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -200,8 +200,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
break;
case BCM6362_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6362_REG;
- irq_mask_addr += PERF_IRQMASK_6362_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
+ irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -210,8 +210,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
break;
case BCM6368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6368_REG;
- irq_mask_addr += PERF_IRQMASK_6368_REG;
+ irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
+ irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;
@@ -271,8 +271,8 @@ void __dispatch_internal_##width(void)
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
- val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
- val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
+ val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \
+ val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \
pending[--tgt] = val; \
\
if (val) \
@@ -299,9 +299,9 @@ static void __internal_irq_mask_##width(
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
@@ -310,9 +310,9 @@ static void __internal_irq_unmask_##widt
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
val |= (1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
}
BUILD_IPIC_INTERNAL(32);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -215,23 +215,23 @@
/* Interrupt Mask register */
#define PERF_IRQMASK_3368_REG 0xc
-#define PERF_IRQMASK_6328_REG 0x20
+#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
#define PERF_IRQMASK_6338_REG 0xc
#define PERF_IRQMASK_6345_REG 0xc
#define PERF_IRQMASK_6348_REG 0xc
-#define PERF_IRQMASK_6358_REG 0xc
-#define PERF_IRQMASK_6362_REG 0x20
-#define PERF_IRQMASK_6368_REG 0x20
+#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
+#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
+#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
/* Interrupt Status register */
#define PERF_IRQSTAT_3368_REG 0x10
-#define PERF_IRQSTAT_6328_REG 0x28
+#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
#define PERF_IRQSTAT_6338_REG 0x10
#define PERF_IRQSTAT_6345_REG 0x10
#define PERF_IRQSTAT_6348_REG 0x10
-#define PERF_IRQSTAT_6358_REG 0x10
-#define PERF_IRQSTAT_6362_REG 0x28
-#define PERF_IRQSTAT_6368_REG 0x28
+#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
+#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
+#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
/* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG_3368 0x14

89
target/linux/brcm63xx/patches-3.10/315-MIPS-BCM63XX-remove-RUNTIME_DETECT-usage-from-enet-c.patch Normal file
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@ -0,0 +1,89 @@
From ed6c71de07ad042691ec02e9eb97375ddc91ed01 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Dec 2013 13:45:22 +0100
Subject: [PATCH 6/8] MIPS: BCM63XX: remove !RUNTIME_DETECT usage from enet
code
---
arch/mips/bcm63xx/dev-enet.c | 4 --
.../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 46 ----------------------
2 files changed, 50 deletions(-)
--- a/arch/mips/bcm63xx/dev-enet.c
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -14,7 +14,6 @@
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
-#ifdef BCMCPU_RUNTIME_DETECT
static const unsigned long bcm6348_regs_enetdmac[] = {
[ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
[ENETDMAC_IR] = ENETDMAC_IR_REG,
@@ -43,9 +42,6 @@ static __init void bcm63xx_enetdmac_regs
else
bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac;
}
-#else
-static __init void bcm63xx_enetdmac_regs_init(void) { }
-#endif
static struct resource shared_res[] = {
{
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -112,55 +112,9 @@ enum bcm63xx_regs_enetdmac {
static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
{
-#ifdef BCMCPU_RUNTIME_DETECT
extern const unsigned long *bcm63xx_regs_enetdmac;
return bcm63xx_regs_enetdmac[reg];
-#else
-#ifdef CONFIG_BCM63XX_CPU_6345
- switch (reg) {
- case ENETDMAC_CHANCFG:
- return ENETDMA_6345_CHANCFG_REG;
- case ENETDMAC_IR:
- return ENETDMA_6345_IR_REG;
- case ENETDMAC_IRMASK:
- return ENETDMA_6345_IRMASK_REG;
- case ENETDMAC_MAXBURST:
- return ENETDMA_6345_MAXBURST_REG;
- case ENETDMAC_BUFALLOC:
- return ENETDMA_6345_BUFALLOC_REG;
- case ENETDMAC_RSTART:
- return ENETDMA_6345_RSTART_REG;
- case ENETDMAC_FC:
- return ENETDMA_6345_FC_REG;
- case ENETDMAC_LEN:
- return ENETDMA_6345_LEN_REG;
- }
-#endif
-#if defined(CONFIG_BCM63XX_CPU_6328) || \
- defined(CONFIG_BCM63XX_CPU_6338) || \
- defined(CONFIG_BCM63XX_CPU_6348) || \
- defined(CONFIG_BCM63XX_CPU_6358) || \
- defined(CONFIG_BCM63XX_CPU_6362) || \
- defined(CONFIG_BCM63XX_CPU_6368)
- switch (reg) {
- case ENETDMAC_CHANCFG:
- return ENETDMAC_CHANCFG_REG;
- case ENETDMAC_IR:
- return ENETDMAC_IR_REG;
- case ENETDMAC_IRMASK:
- return ENETDMAC_IRMASK_REG;
- case ENETDMAC_MAXBURST:
- return ENETDMAC_MAXBURST_REG;
- case ENETDMAC_BUFALLOC:
- case ENETDMAC_RSTART:
- case ENETDMAC_FC:
- case ENETDMAC_LEN:
- return 0;
- }
-#endif
-#endif
- return 0;
}

186
target/linux/brcm63xx/patches-3.10/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch
View file

@ -1,186 +0,0 @@
From 1a1769d6268c93b042f635b31b43024fea7feb30 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:31:29 +0200
Subject: [PATCH 08/14] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
second pin
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_3368
#define irq_stat_reg0 PERF_IRQSTAT_3368_REG
#define irq_mask_reg0 PERF_IRQMASK_3368_REG
+#define irq_stat_reg1 0
+#define irq_mask_reg1 0
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6328
#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
+#define irq_stat_reg1 PERF_IRQSTAT_6328_REG(1)
+#define irq_mask_reg1 PERF_IRQMASK_6328_REG(1)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6338
#define irq_stat_reg0 PERF_IRQSTAT_6338_REG
#define irq_mask_reg0 PERF_IRQMASK_6338_REG
+#define irq_stat_reg1 0
+#define irq_mask_reg1 0
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6345
#define irq_stat_reg0 PERF_IRQSTAT_6345_REG
#define irq_mask_reg0 PERF_IRQMASK_6345_REG
+#define irq_stat_reg1 0
+#define irq_mask_reg1 0
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6348
#define irq_stat_reg0 PERF_IRQSTAT_6348_REG
#define irq_mask_reg0 PERF_IRQMASK_6348_REG
+#define irq_stat_reg1 0
+#define irq_mask_reg1 0
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6358
#define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
+#define irq_stat_reg1 PERF_IRQSTAT_6358_REG(1)
+#define irq_mask_reg1 PERF_IRQMASK_6358_REG(1)
#define irq_bits 32
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6362
#define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
+#define irq_stat_reg1 PERF_IRQSTAT_6362_REG(1)
+#define irq_mask_reg1 PERF_IRQMASK_6362_REG(1)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -107,6 +121,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6368
#define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
+#define irq_stat_reg1 PERF_IRQSTAT_6368_REG(1)
+#define irq_mask_reg1 PERF_IRQMASK_6368_REG(1)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
@@ -128,13 +144,20 @@ static void __internal_irq_unmask_64(uns
#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
+#if (irq_stat_reg1 > 0) && (irq_mask_reg1 > 0)
+#define irq_stat_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1)
+#define irq_mask_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1)
+#else
+#define irq_stat_addr1 0
+#define irq_mask_addr1 0
+#endif
static inline void bcm63xx_init_irq(void)
{
}
#else /* ! BCMCPU_RUNTIME_DETECT */
-static u32 irq_stat_addr0, irq_mask_addr0;
+static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
@@ -149,11 +172,15 @@ static void bcm63xx_init_irq(void)
irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
+ irq_stat_addr1 = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
irq_mask_addr0 += PERF_IRQMASK_3368_REG;
+ irq_stat_addr1 = 0;
+ irq_stat_addr1 = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
@@ -161,6 +188,8 @@ static void bcm63xx_init_irq(void)
case BCM6328_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
+ irq_stat_addr1 += PERF_IRQSTAT_6328_REG(1);
+ irq_stat_addr1 += PERF_IRQMASK_6328_REG(1);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -171,6 +200,8 @@ static void bcm63xx_init_irq(void)
case BCM6338_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
irq_mask_addr0 += PERF_IRQMASK_6338_REG;
+ irq_stat_addr1 = 0;
+ irq_mask_addr1 = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
@@ -178,6 +209,8 @@ static void bcm63xx_init_irq(void)
case BCM6345_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
irq_mask_addr0 += PERF_IRQMASK_6345_REG;
+ irq_stat_addr1 = 0;
+ irq_mask_addr1 = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
@@ -185,6 +218,8 @@ static void bcm63xx_init_irq(void)
case BCM6348_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
irq_mask_addr0 += PERF_IRQMASK_6348_REG;
+ irq_stat_addr1 = 0;
+ irq_mask_addr1 = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
@@ -192,6 +227,8 @@ static void bcm63xx_init_irq(void)
case BCM6358_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
+ irq_stat_addr1 += PERF_IRQSTAT_6358_REG(1);
+ irq_mask_addr1 += PERF_IRQMASK_6358_REG(1);
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -202,6 +239,8 @@ static void bcm63xx_init_irq(void)
case BCM6362_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
+ irq_stat_addr1 += PERF_IRQSTAT_6362_REG(1);
+ irq_mask_addr1 += PERF_IRQMASK_6362_REG(1);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -212,6 +251,8 @@ static void bcm63xx_init_irq(void)
case BCM6368_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
+ irq_stat_addr1 += PERF_IRQSTAT_6368_REG(1);
+ irq_mask_addr1 += PERF_IRQMASK_6368_REG(1);
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;

23
target/linux/brcm63xx/patches-3.10/316-MIPS-BCM63XX-remove-RUNTIME_DETECT-in-cpu-feature-ov.patch Normal file
View file

@ -0,0 +1,23 @@
From 12c6957004d6770f4b34d59d8a3cafd5d8bfce15 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Dec 2013 14:06:12 +0100
Subject: [PATCH 7/8] MIPS: BCM63XX: remove !RUNTIME_DETECT in
cpu-feature-overrides
All three SoCs have in common they have a BMIPS32/BMIPS3300 CPU, so
we can replace this as no SoC with BMIPS4350 support enabled.
---
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -24,7 +24,7 @@
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
-#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCM63XX_CPU_6348) || defined(CONFIG_BCM63XX_CPU_6345) || defined(CONFIG_BCM63XX_CPU_6338))
+#if !defined(CONFIG_SYS_HAS_CPU_BMIPS4350)
#define cpu_has_dc_aliases 0
#endif

199
target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-remove-RUNTIME_DETECT-code-for-bcmcpu_g.patch Normal file
View file

@ -0,0 +1,199 @@
From 78c3d2e796a28ad55f6c2310a11ab22e91bb52fc Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Mon, 2 Dec 2013 12:30:44 +0100
Subject: [PATCH 8/8] MIPS: BCM63XX: remove !RUNTIME_DETECT code for
bcmcpu_get_id
Use the same pattern as with get_*_cpu_type() to allow the compiler
to remove code for non enabled devices.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/cpu.c | 11 +--
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 120 +++++++----------------
2 files changed, 38 insertions(+), 93 deletions(-)
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -24,7 +24,9 @@ EXPORT_SYMBOL(bcm63xx_regs_base);
const int *bcm63xx_irqs;
EXPORT_SYMBOL(bcm63xx_irqs);
-static u16 bcm63xx_cpu_id;
+u16 bcm63xx_cpu_id __read_mostly;
+EXPORT_SYMBOL(bcm63xx_cpu_id);
+
static u8 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;
@@ -97,13 +99,6 @@ static const int bcm6368_irqs[] = {
};
-u16 __bcm63xx_get_cpu_id(void)
-{
- return bcm63xx_cpu_id;
-}
-
-EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
-
u8 bcm63xx_get_cpu_rev(void)
{
return bcm63xx_cpu_rev;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -19,118 +19,68 @@
#define BCM6368_CPU_ID 0x6368
void __init bcm63xx_cpu_init(void);
-u16 __bcm63xx_get_cpu_id(void);
u8 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);
+static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
+{
+ switch (cpu_id) {
#ifdef CONFIG_BCM63XX_CPU_3368
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
-# endif
-# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
-#else
-# define BCMCPU_IS_3368() (0)
+ case BCM3368_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6328
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
-# endif
-# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
-#else
-# define BCMCPU_IS_6328() (0)
+ case BCM6328_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6338
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
-# endif
-# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
-#else
-# define BCMCPU_IS_6338() (0)
+ case BCM6338_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
-# endif
-# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
-#else
-# define BCMCPU_IS_6345() (0)
+ case BCM6345_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
-# endif
-# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
-#else
-# define BCMCPU_IS_6348() (0)
+ case BCM6348_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
-# endif
-# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
-#else
-# define BCMCPU_IS_6358() (0)
+ case BCM6358_CPU_ID:
#endif
#ifdef CONFIG_BCM63XX_CPU_6362
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
-# endif
-# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
-#else
-# define BCMCPU_IS_6362() (0)
+ case BCM6362_CPU_ID:
#endif
-
#ifdef CONFIG_BCM63XX_CPU_6368
-# ifdef bcm63xx_get_cpu_id
-# undef bcm63xx_get_cpu_id
-# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-# define BCMCPU_RUNTIME_DETECT
-# else
-# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
-# endif
-# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
-#else
-# define BCMCPU_IS_6368() (0)
-#endif
-
-#ifndef bcm63xx_get_cpu_id
-#error "No CPU support configured"
+ case BCM6368_CPU_ID:
#endif
+ break;
+ default:
+ unreachable();
+ }
+
+ return cpu_id;
+}
+
+extern u16 bcm63xx_cpu_id;
+
+static inline u16 __pure bcm63xx_get_cpu_id(void)
+{
+ const u16 cpu_id = bcm63xx_cpu_id;
+
+ return __bcm63xx_get_cpu_id(cpu_id);
+}
+
+#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
+#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
+#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+#define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
+#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
+#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
+#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
/*
* While registers sets are (mostly) the same across 63xx CPU, base

80
target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch
View file

@ -1,80 +0,0 @@
From 353f07637d82cf485a9319d203a6ed9b38590526 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 15:35:12 +0200
Subject: [PATCH 09/14] MIPS: BCM63XX: use a helper for getting the right
register address
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 30 ++++++++++++++++++++++++------
1 file changed, 24 insertions(+), 6 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -284,6 +284,20 @@ static inline u32 get_ext_irq_perf_reg(i
return ext_irq_cfg_reg2;
}
+static inline u32 get_irq_stat_addr(int pin)
+{
+ if (pin == 0)
+ return irq_stat_addr0;
+ return irq_stat_addr1;
+}
+
+static inline u32 get_irq_mask_addr(int pin)
+{
+ if (pin == 0)
+ return irq_mask_addr0;
+ return irq_mask_addr1;
+}
+
static inline void handle_internal(int intbit)
{
if (is_ext_irq_cascaded &&
@@ -307,13 +321,15 @@ void __dispatch_internal_##width(void)
unsigned int src, tgt; \
bool irqs_pending = false; \
static int i; \
+ u32 irq_stat_addr = get_irq_stat_addr(0); \
+ u32 irq_mask_addr = get_irq_mask_addr(0); \
\
/* read registers in reverse order */ \
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
- val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \
- val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \
+ val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
+ val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
pending[--tgt] = val; \
\
if (val) \
@@ -339,10 +355,11 @@ static void __internal_irq_mask_##width(
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
+ u32 irq_mask_addr = get_irq_mask_addr(0); \
\
- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
@@ -350,10 +367,11 @@ static void __internal_irq_unmask_##widt
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
+ u32 irq_mask_addr = get_irq_mask_addr(0); \
\
- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
val |= (1 << bit); \
- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
}
BUILD_IPIC_INTERNAL(32);

73
target/linux/brcm63xx/patches-3.10/318-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch
View file

@ -1,73 +0,0 @@
From b6b668f780d62d41bc14bc7baba1692e17cabf84 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 11:21:16 +0200
Subject: [PATCH 10/14] MIPS: BCM63XX: add cpu argument to dispatch internal
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,8 +19,8 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
-static void __dispatch_internal_32(void) __maybe_unused;
-static void __dispatch_internal_64(void) __maybe_unused;
+static void __dispatch_internal_32(int cpu) __maybe_unused;
+static void __dispatch_internal_64(int cpu) __maybe_unused;
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
@@ -158,7 +158,7 @@ static inline void bcm63xx_init_irq(void
#else /* ! BCMCPU_RUNTIME_DETECT */
static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
-static void (*dispatch_internal)(void);
+static void (*dispatch_internal)(int cpu);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
@@ -315,14 +315,15 @@ static inline void handle_internal(int i
*/
#define BUILD_IPIC_INTERNAL(width) \
-void __dispatch_internal_##width(void) \
+void __dispatch_internal_##width(int cpu) \
{ \
u32 pending[width / 32]; \
unsigned int src, tgt; \
bool irqs_pending = false; \
- static int i; \
- u32 irq_stat_addr = get_irq_stat_addr(0); \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
+ static int i[NR_CPUS]; \
+ u32 irq_stat_addr = get_irq_stat_addr(cpu); \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
+ int *next = &i[cpu]; \
\
/* read registers in reverse order */ \
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
@@ -340,9 +341,9 @@ void __dispatch_internal_##width(void)
return; \
\
while (1) { \
- int to_call = i; \
+ int to_call = *next; \
\
- i = (i + 1) & (width - 1); \
+ *next = (*next + 1) & (width - 1); \
if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
handle_internal(to_call); \
break; \
@@ -394,7 +395,7 @@ asmlinkage void plat_irq_dispatch(void)
if (cause & CAUSEF_IP1)
do_IRQ(1);
if (cause & CAUSEF_IP2)
- dispatch_internal();
+ dispatch_internal(0);
if (!is_ext_irq_cascaded) {
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);

21
target/linux/brcm63xx/patches-3.10/313-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch → target/linux/brcm63xx/patches-3.10/318-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch
View file

@ -1,15 +1,15 @@
From 3bc62bd6e8c8a37d64cb797d24955711e98de15c Mon Sep 17 00:00:00 2001
From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 21 Mar 2013 17:05:15 +0100
Subject: [PATCH 05/14] MIPS: BCM63XX: rename __dispatch_internal to
Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to
__dispatch_internal_32
Make it follow the same naming convention as the other functions.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
arch/mips/bcm63xx/irq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@ -22,16 +22,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
static void __dispatch_internal_64(void) __maybe_unused;
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
@@ -117,7 +117,7 @@ static void __internal_irq_unmask_64(uns
#endif
#if irq_bits == 32
-#define dispatch_internal __dispatch_internal
+#define dispatch_internal __dispatch_internal_32
#define internal_irq_mask __internal_irq_mask_32
#define internal_irq_unmask __internal_irq_unmask_32
#else
@@ -225,7 +225,7 @@ static void bcm63xx_init_irq(void)
@@ -117,7 +117,7 @@ static void bcm63xx_init_irq(void)
}
if (irq_bits == 32) {
@ -40,7 +31,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
internal_irq_mask = __internal_irq_mask_32;
internal_irq_unmask = __internal_irq_unmask_32;
} else {
@@ -258,7 +258,7 @@ static inline void handle_internal(int i
@@ -149,7 +149,7 @@ static inline void handle_internal(int i
* will resume the loop where it ended the last time we left this
* function.
*/

223
target/linux/brcm63xx/patches-3.10/319-MIPS-BCM63XX-move-bcm63xx_init_irq-down.patch Normal file
View file

@ -0,0 +1,223 @@
From c28c639b031385ecf965eecf3bfb532e88044c89 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 15 Dec 2013 20:52:53 +0100
Subject: [PATCH 30/53] MIPS: BCM63XX: move bcm63xx_init_irq down
Allows up to drop the prototypes from the top.
---
arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++-------------------------
1 file changed, 92 insertions(+), 98 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,13 +19,6 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
-static void __dispatch_internal_32(void) __maybe_unused;
-static void __dispatch_internal_64(void) __maybe_unused;
-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-
static u32 irq_stat_addr, irq_mask_addr;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
@@ -35,97 +28,6 @@ static unsigned int ext_irq_cfg_reg1, ex
static void (*internal_irq_mask)(unsigned int irq);
static void (*internal_irq_unmask)(unsigned int irq);
-static void bcm63xx_init_irq(void)
-{
- int irq_bits;
-
- irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
-
- switch (bcm63xx_get_cpu_id()) {
- case BCM3368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_3368_REG;
- irq_mask_addr += PERF_IRQMASK_3368_REG;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
- break;
- case BCM6328_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6328_REG;
- irq_mask_addr += PERF_IRQMASK_6328_REG;
- irq_bits = 64;
- ext_irq_count = 4;
- is_ext_irq_cascaded = 1;
- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
- break;
- case BCM6338_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6338_REG;
- irq_mask_addr += PERF_IRQMASK_6338_REG;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
- break;
- case BCM6345_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6345_REG;
- irq_mask_addr += PERF_IRQMASK_6345_REG;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
- break;
- case BCM6348_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6348_REG;
- irq_mask_addr += PERF_IRQMASK_6348_REG;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
- break;
- case BCM6358_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6358_REG;
- irq_mask_addr += PERF_IRQMASK_6358_REG;
- irq_bits = 32;
- ext_irq_count = 4;
- is_ext_irq_cascaded = 1;
- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
- break;
- case BCM6362_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6362_REG;
- irq_mask_addr += PERF_IRQMASK_6362_REG;
- irq_bits = 64;
- ext_irq_count = 4;
- is_ext_irq_cascaded = 1;
- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
- break;
- case BCM6368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6368_REG;
- irq_mask_addr += PERF_IRQMASK_6368_REG;
- irq_bits = 64;
- ext_irq_count = 6;
- is_ext_irq_cascaded = 1;
- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
- break;
- default:
- BUG();
- }
-
- if (irq_bits == 32) {
- dispatch_internal = __dispatch_internal_32;
- internal_irq_mask = __internal_irq_mask_32;
- internal_irq_unmask = __internal_irq_unmask_32;
- } else {
- dispatch_internal = __dispatch_internal_64;
- internal_irq_mask = __internal_irq_mask_64;
- internal_irq_unmask = __internal_irq_unmask_64;
- }
-}
static inline u32 get_ext_irq_perf_reg(int irq)
{
@@ -451,6 +353,98 @@ static struct irqaction cpu_ext_cascade_
.flags = IRQF_NO_THREAD,
};
+static void bcm63xx_init_irq(void)
+{
+ int irq_bits;
+
+ irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+ switch (bcm63xx_get_cpu_id()) {
+ case BCM3368_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_3368_REG;
+ irq_mask_addr += PERF_IRQMASK_3368_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
+ break;
+ case BCM6328_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6328_REG;
+ irq_mask_addr += PERF_IRQMASK_6328_REG;
+ irq_bits = 64;
+ ext_irq_count = 4;
+ is_ext_irq_cascaded = 1;
+ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
+ break;
+ case BCM6338_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6338_REG;
+ irq_mask_addr += PERF_IRQMASK_6338_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
+ break;
+ case BCM6345_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6345_REG;
+ irq_mask_addr += PERF_IRQMASK_6345_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
+ break;
+ case BCM6348_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6348_REG;
+ irq_mask_addr += PERF_IRQMASK_6348_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+ break;
+ case BCM6358_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6358_REG;
+ irq_mask_addr += PERF_IRQMASK_6358_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ is_ext_irq_cascaded = 1;
+ ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+ ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+ break;
+ case BCM6362_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6362_REG;
+ irq_mask_addr += PERF_IRQMASK_6362_REG;
+ irq_bits = 64;
+ ext_irq_count = 4;
+ is_ext_irq_cascaded = 1;
+ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
+ break;
+ case BCM6368_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6368_REG;
+ irq_mask_addr += PERF_IRQMASK_6368_REG;
+ irq_bits = 64;
+ ext_irq_count = 6;
+ is_ext_irq_cascaded = 1;
+ ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+ ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+ ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
+ break;
+ default:
+ BUG();
+ }
+
+ if (irq_bits == 32) {
+ dispatch_internal = __dispatch_internal_32;
+ internal_irq_mask = __internal_irq_mask_32;
+ internal_irq_unmask = __internal_irq_unmask_32;
+ } else {
+ dispatch_internal = __dispatch_internal_64;
+ internal_irq_mask = __internal_irq_mask_64;
+ internal_irq_unmask = __internal_irq_unmask_64;
+ }
+}
+
void __init arch_init_irq(void)
{
int i;

12
target/linux/brcm63xx/patches-3.10/314-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch → target/linux/brcm63xx/patches-3.10/320-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch
View file

@ -1,8 +1,8 @@
From 7447daa9a0768db157bbb64585f5411389712d59 Mon Sep 17 00:00:00 2001
From 01bf26c51b427e24ac69f604d33f7d9360a9e470 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 18 Apr 2013 21:14:49 +0200
Subject: [PATCH 06/14] MIPS: BCM63XX: replace irq dispatch code with a
generic version
Subject: [PATCH 31/53] MIPS: BCM63XX: replace irq dispatch code with a generic
version
The generic version uses a variable length of u32 registers of u32/u64.
This allows easier support for longer registers without having to rewrite
@ -13,12 +13,12 @@ This "generic" version is not slower than the old version in the best case
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 130 ++++++++++++++++++++---------------------------
arch/mips/bcm63xx/irq.c | 130 +++++++++++++++++++++---------------------------
1 file changed, 56 insertions(+), 74 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -258,47 +258,65 @@ static inline void handle_internal(int i
@@ -51,47 +51,65 @@ static inline void handle_internal(int i
* will resume the loop where it ended the last time we left this
* function.
*/
@ -122,7 +122,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
asmlinkage void plat_irq_dispatch(void)
{
@@ -335,42 +353,6 @@ asmlinkage void plat_irq_dispatch(void)
@@ -128,42 +146,6 @@ asmlinkage void plat_irq_dispatch(void)
* internal IRQs operations: only mask/unmask on PERF irq mask
* register.
*/

183
target/linux/brcm63xx/patches-3.10/321-MIPS-BCM63XX-append-irq-line-number-to-irq_-stat-mas.patch Normal file
View file

@ -0,0 +1,183 @@
From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:24:06 +0200
Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
irq_{stat,mask}*
The SMP capable irq controllers have two interupt output pins which are
controlled through separate registers, so make the variables arrays.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 51 ++++++++++++-----------
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++----
2 files changed, 34 insertions(+), 33 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,7 +19,8 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
-static u32 irq_stat_addr, irq_mask_addr;
+static u32 irq_stat_addr[2];
+static u32 irq_mask_addr[2];
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
@@ -64,8 +65,8 @@ void __dispatch_internal_##width(void)
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
- val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
- val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
+ val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
+ val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
pending[--tgt] = val; \
\
if (val) \
@@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
@@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val |= (1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
}
BUILD_IPIC_INTERNAL(32);
@@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
{
int irq_bits;
- irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+ irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_3368_REG;
- irq_mask_addr += PERF_IRQMASK_3368_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
+ irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
break;
case BCM6328_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6328_REG;
- irq_mask_addr += PERF_IRQMASK_6328_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
+ irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
break;
case BCM6338_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6338_REG;
- irq_mask_addr += PERF_IRQMASK_6338_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
+ irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
break;
case BCM6345_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6345_REG;
- irq_mask_addr += PERF_IRQMASK_6345_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
+ irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
break;
case BCM6348_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6348_REG;
- irq_mask_addr += PERF_IRQMASK_6348_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
+ irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
break;
case BCM6358_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6358_REG;
- irq_mask_addr += PERF_IRQMASK_6358_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
+ irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
break;
case BCM6362_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6362_REG;
- irq_mask_addr += PERF_IRQMASK_6362_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
+ irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
break;
case BCM6368_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6368_REG;
- irq_mask_addr += PERF_IRQMASK_6368_REG;
+ irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
+ irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -215,23 +215,23 @@
/* Interrupt Mask register */
#define PERF_IRQMASK_3368_REG 0xc
-#define PERF_IRQMASK_6328_REG 0x20
+#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
#define PERF_IRQMASK_6338_REG 0xc
#define PERF_IRQMASK_6345_REG 0xc
#define PERF_IRQMASK_6348_REG 0xc
-#define PERF_IRQMASK_6358_REG 0xc
-#define PERF_IRQMASK_6362_REG 0x20
-#define PERF_IRQMASK_6368_REG 0x20
+#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
+#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
+#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
/* Interrupt Status register */
#define PERF_IRQSTAT_3368_REG 0x10
-#define PERF_IRQSTAT_6328_REG 0x28
+#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
#define PERF_IRQSTAT_6338_REG 0x10
#define PERF_IRQSTAT_6345_REG 0x10
#define PERF_IRQSTAT_6348_REG 0x10
-#define PERF_IRQSTAT_6358_REG 0x10
-#define PERF_IRQSTAT_6362_REG 0x28
-#define PERF_IRQSTAT_6368_REG 0x28
+#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
+#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
+#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
/* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG_3368 0x14

92
target/linux/brcm63xx/patches-3.10/322-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch Normal file
View file

@ -0,0 +1,92 @@
From 842f213228e6fc9fd6cca01ab5128623112aa7a9 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:31:29 +0200
Subject: [PATCH 33/53] MIPS: BCM63XX: populate irq_{stat,mask}_addr for second
pin
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -342,11 +342,15 @@ static void bcm63xx_init_irq(void)
irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
+ irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
+ irq_stat_addr[1] = 0;
+ irq_stat_addr[1] = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
@@ -354,6 +358,8 @@ static void bcm63xx_init_irq(void)
case BCM6328_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
+ irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
+ irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -364,6 +370,8 @@ static void bcm63xx_init_irq(void)
case BCM6338_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
+ irq_stat_addr[1] = 0;
+ irq_mask_addr[1] = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
@@ -371,6 +379,8 @@ static void bcm63xx_init_irq(void)
case BCM6345_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
+ irq_stat_addr[1] = 0;
+ irq_mask_addr[1] = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
@@ -378,6 +388,8 @@ static void bcm63xx_init_irq(void)
case BCM6348_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
+ irq_stat_addr[1] = 0;
+ irq_mask_addr[1] = 0;
irq_bits = 32;
ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
@@ -385,6 +397,8 @@ static void bcm63xx_init_irq(void)
case BCM6358_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
+ irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
+ irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -395,6 +409,8 @@ static void bcm63xx_init_irq(void)
case BCM6362_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
+ irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
+ irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
@@ -405,6 +421,8 @@ static void bcm63xx_init_irq(void)
case BCM6368_CPU_ID:
irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
+ irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
+ irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;

70
target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch Normal file
View file

@ -0,0 +1,70 @@
From a33bb660c712447ba8b561109cda6734954a6efa Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 11:21:16 +0200
Subject: [PATCH 34/53] MIPS: BCM63XX: add pin argument to dispatch internal
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,9 +19,10 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
+
static u32 irq_stat_addr[2];
static u32 irq_mask_addr[2];
-static void (*dispatch_internal)(void);
+static void (*dispatch_internal)(int pin);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
@@ -54,19 +55,20 @@ static inline void handle_internal(int i
*/
#define BUILD_IPIC_INTERNAL(width) \
-void __dispatch_internal_##width(void) \
+void __dispatch_internal_##width(int pin) \
{ \
u32 pending[width / 32]; \
unsigned int src, tgt; \
bool irqs_pending = false; \
- static int i; \
+ static int i[2]; \
+ int *next = &i[pin]; \
\
/* read registers in reverse order */ \
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
+ val = bcm_readl(irq_stat_addr[pin] + src * sizeof(u32)); \
+ val &= bcm_readl(irq_mask_addr[pin] + src * sizeof(u32)); \
pending[--tgt] = val; \
\
if (val) \
@@ -77,9 +79,9 @@ void __dispatch_internal_##width(void)
return; \
\
while (1) { \
- int to_call = i; \
+ int to_call = *next; \
\
- i = (i + 1) & (width - 1); \
+ *next = (*next + 1) & (width - 1); \
if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
handle_internal(to_call); \
break; \
@@ -129,7 +131,7 @@ asmlinkage void plat_irq_dispatch(void)
if (cause & CAUSEF_IP1)
do_IRQ(1);
if (cause & CAUSEF_IP2)
- dispatch_internal();
+ dispatch_internal(0);
if (!is_ext_irq_cascaded) {
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);

62
target/linux/brcm63xx/patches-3.10/319-MIPS-BCM63XX-protect-irq-register-accesses.patch → target/linux/brcm63xx/patches-3.10/324-MIPS-BCM63XX-protect-irq-register-accesses.patch
View file

@ -1,10 +1,10 @@
From 05e32e9dc84ee96728596c0b8b86de7eae8de229 Mon Sep 17 00:00:00 2001
From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 21 Apr 2013 15:38:56 +0200
Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
---
arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
--- a/arch/mips/bcm63xx/irq.c
@ -17,20 +17,20 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
@@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
@@ -20,6 +21,9 @@
#include <bcm63xx_irq.h>
+static DEFINE_SPINLOCK(ipic_lock);
+static DEFINE_SPINLOCK(epic_lock);
+
#ifndef BCMCPU_RUNTIME_DETECT
#ifdef CONFIG_BCM63XX_CPU_3368
#define irq_stat_reg0 PERF_IRQSTAT_3368_REG
@@ -324,8 +328,10 @@ void __dispatch_internal_##width(int cpu
u32 irq_stat_addr = get_irq_stat_addr(cpu); \
u32 irq_mask_addr = get_irq_mask_addr(cpu); \
int *next = &i[cpu]; \
static u32 irq_stat_addr[2];
static u32 irq_mask_addr[2];
static void (*dispatch_internal)(int pin);
@@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin
bool irqs_pending = false; \
static int i[2]; \
int *next = &i[pin]; \
+ unsigned long flags; \
\
/* read registers in reverse order */ \
@ -38,7 +38,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
@@ -336,6 +342,7 @@ void __dispatch_internal_##width(int cpu
@@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin
if (val) \
irqs_pending = true; \
} \
@ -46,35 +46,35 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
\
if (!irqs_pending) \
return; \
@@ -357,10 +364,13 @@ static void __internal_irq_mask_##width(
@@ -94,10 +101,13 @@ static void __internal_irq_mask_##width(
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
u32 irq_mask_addr = get_irq_mask_addr(0); \
+ unsigned long flags; \
\
+ spin_lock_irqsave(&ipic_lock, flags); \
val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val &= ~(1 << bit); \
bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
+ spin_unlock_irqrestore(&ipic_lock, flags); \
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
@@ -369,10 +379,13 @@ static void __internal_irq_unmask_##widt
@@ -105,10 +115,13 @@ static void __internal_irq_unmask_##widt
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
u32 irq_mask_addr = get_irq_mask_addr(0); \
+ unsigned long flags; \
\
+ spin_lock_irqsave(&ipic_lock, flags); \
val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val |= (1 << bit); \
bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
+ spin_unlock_irqrestore(&ipic_lock, flags); \
}
BUILD_IPIC_INTERNAL(32);
@@ -431,8 +444,10 @@ static void bcm63xx_external_irq_mask(st
@@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(st
{
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
@ -85,7 +85,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
reg = bcm_perf_readl(regaddr);
if (BCMCPU_IS_6348())
@@ -441,6 +456,8 @@ static void bcm63xx_external_irq_mask(st
@@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(st
reg &= ~EXTIRQ_CFG_MASK(irq % 4);
bcm_perf_writel(reg, regaddr);
@ -94,7 +94,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
if (is_ext_irq_cascaded)
internal_irq_mask(irq + ext_irq_start);
}
@@ -449,8 +466,10 @@ static void bcm63xx_external_irq_unmask(
@@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask(
{
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
@ -105,7 +105,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
reg = bcm_perf_readl(regaddr);
if (BCMCPU_IS_6348())
@@ -459,6 +478,7 @@ static void bcm63xx_external_irq_unmask(
@@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask(
reg |= EXTIRQ_CFG_MASK(irq % 4);
bcm_perf_writel(reg, regaddr);
@ -113,7 +113,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
if (is_ext_irq_cascaded)
internal_irq_unmask(irq + ext_irq_start);
@@ -468,8 +488,10 @@ static void bcm63xx_external_irq_clear(s
@@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(s
{
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
@ -124,7 +124,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
reg = bcm_perf_readl(regaddr);
if (BCMCPU_IS_6348())
@@ -478,6 +500,7 @@ static void bcm63xx_external_irq_clear(s
@@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(s
reg |= EXTIRQ_CFG_CLEAR(irq % 4);
bcm_perf_writel(reg, regaddr);
@ -132,7 +132,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
}
static int bcm63xx_external_irq_set_type(struct irq_data *d,
@@ -486,6 +509,7 @@ static int bcm63xx_external_irq_set_type
@@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type
unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
u32 reg, regaddr;
int levelsense, sense, bothedge;
@ -140,7 +140,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
flow_type &= IRQ_TYPE_SENSE_MASK;
@@ -520,6 +544,7 @@ static int bcm63xx_external_irq_set_type
@@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type
}
regaddr = get_ext_irq_perf_reg(irq);
@ -148,7 +148,7 @@ Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
reg = bcm_perf_readl(regaddr);
irq %= 4;
@@ -564,6 +589,7 @@ static int bcm63xx_external_irq_set_type
@@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type
}
bcm_perf_writel(reg, regaddr);

46
target/linux/brcm63xx/patches-3.10/320-MIPS-BCM63XX-wire-up-the-second-CPU-s-irq-line.patch → target/linux/brcm63xx/patches-3.10/325-MIPS-BCM63XX-wire-up-the-second-cpu-s-irq-line.patch
View file

@ -1,68 +1,60 @@
From 70c33fe0df8d14e40f3ca92ce56a668d66184858 Mon Sep 17 00:00:00 2001
From df6661d1b5c001eb91ce07f364fd5b6468fd6f99 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 12:03:15 +0200
Subject: [PATCH 12/14] MIPS: BCM63XX: wire up the second cpu's irq line
Subject: [PATCH 36/53] MIPS: BCM63XX: wire up the second cpu's irq line
---
arch/mips/bcm63xx/irq.c | 50 ++++++++++++++++++++++++++++++++++++++---------
1 file changed, 41 insertions(+), 9 deletions(-)
arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++-------
1 file changed, 37 insertions(+), 7 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -363,13 +363,20 @@ static void __internal_irq_mask_##width(
u32 val; \
@@ -102,11 +102,17 @@ static void __internal_irq_mask_##width(
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
unsigned long flags; \
+ int cpu; \
\
spin_lock_irqsave(&ipic_lock, flags); \
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
- val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
+ for_each_present_cpu(cpu) { \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
+ \
+ if (!irq_mask_addr) \
+ if (!irq_mask_addr[cpu]) \
+ break; \
+ \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
+ val &= ~(1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
+ } \
spin_unlock_irqrestore(&ipic_lock, flags); \
} \
\
@@ -378,13 +385,23 @@ static void __internal_irq_unmask_##widt
u32 val; \
@@ -116,11 +122,20 @@ static void __internal_irq_unmask_##widt
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
unsigned long flags; \
+ int cpu; \
\
spin_lock_irqsave(&ipic_lock, flags); \
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
- val |= (1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
+ for_each_present_cpu(cpu) { \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
+ \
+ if (!irq_mask_addr) \
+ if (!irq_mask_addr[cpu]) \
+ break; \
+ \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
+ if (cpu_online(cpu)) \
+ val |= (1 << bit); \
+ else \
+ val &= ~(1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
+ } \
spin_unlock_irqrestore(&ipic_lock, flags); \
}
@@ -409,7 +426,10 @@ asmlinkage void plat_irq_dispatch(void)
@@ -145,7 +160,10 @@ asmlinkage void plat_irq_dispatch(void)
do_IRQ(1);
if (cause & CAUSEF_IP2)
dispatch_internal(0);
@ -74,7 +66,7 @@ Subject: [PATCH 12/14] MIPS: BCM63XX: wire up the second cpu's irq line
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
if (cause & CAUSEF_IP4)
@@ -622,6 +642,14 @@ static struct irqaction cpu_ip2_cascade_
@@ -358,6 +376,14 @@ static struct irqaction cpu_ip2_cascade_
.flags = IRQF_NO_THREAD,
};
@ -89,7 +81,7 @@ Subject: [PATCH 12/14] MIPS: BCM63XX: wire up the second cpu's irq line
static struct irqaction cpu_ext_cascade_action = {
.handler = no_action,
.name = "cascade_extirq",
@@ -648,4 +676,8 @@ void __init arch_init_irq(void)
@@ -494,4 +520,8 @@ void __init arch_init_irq(void)
}
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);

39
target/linux/brcm63xx/patches-3.10/321-MIPS-BCM63XX-use-irq_desc-as-argument-for-un-mask.patch → target/linux/brcm63xx/patches-3.10/326-MIPS-BCM63XX-use-irq_desc-as-argument-for-un-mask.patch
View file

@ -1,34 +1,19 @@
From 0e692ab15a69ac4534c18e67ed3cb7685f728037 Mon Sep 17 00:00:00 2001
From b665117faa0dfde70689502fc420d72bbf8e6bd4 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 30 Apr 2013 11:26:53 +0200
Subject: [PATCH 13/14] MIPS: BCM63XX: use irq_desc as argument for (un)mask
Subject: [PATCH 37/53] MIPS: BCM63XX: use irq_desc as argument for (un)mask
In preparation for applying affinity, use the irq descriptor as the
argument for (un)mask.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
arch/mips/bcm63xx/irq.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -22,10 +22,10 @@
static void __dispatch_internal_32(int cpu) __maybe_unused;
static void __dispatch_internal_64(int cpu) __maybe_unused;
-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+static void __internal_irq_mask_32(struct irq_data *d) __maybe_unused;
+static void __internal_irq_mask_64(struct irq_data *d) __maybe_unused;
+static void __internal_irq_unmask_32(struct irq_data *d) __maybe_unused;
+static void __internal_irq_unmask_64(struct irq_data *d) __maybe_unused;
static DEFINE_SPINLOCK(ipic_lock);
static DEFINE_SPINLOCK(epic_lock);
@@ -167,8 +167,8 @@ static int is_ext_irq_cascaded;
@@ -31,8 +31,8 @@ static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
@ -37,9 +22,9 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+static void (*internal_irq_mask)(struct irq_data *d);
+static void (*internal_irq_unmask)(struct irq_data *d);
static void bcm63xx_init_irq(void)
{
@@ -358,9 +358,10 @@ void __dispatch_internal_##width(int cpu
static inline u32 get_ext_irq_perf_reg(int irq)
@@ -96,9 +96,10 @@ void __dispatch_internal_##width(int pin
} \
} \
\
@ -51,7 +36,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
unsigned long flags; \
@@ -380,9 +381,10 @@ static void __internal_irq_mask_##width(
@@ -116,9 +117,10 @@ static void __internal_irq_mask_##width(
spin_unlock_irqrestore(&ipic_lock, flags); \
} \
\
@ -63,7 +48,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
unsigned long flags; \
@@ -448,12 +450,12 @@ asmlinkage void plat_irq_dispatch(void)
@@ -182,12 +184,12 @@ asmlinkage void plat_irq_dispatch(void)
*/
static void bcm63xx_internal_irq_mask(struct irq_data *d)
{
@ -78,7 +63,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
}
/*
@@ -479,7 +481,7 @@ static void bcm63xx_external_irq_mask(st
@@ -213,7 +215,7 @@ static void bcm63xx_external_irq_mask(st
spin_unlock_irqrestore(&epic_lock, flags);
if (is_ext_irq_cascaded)
@ -87,7 +72,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
}
static void bcm63xx_external_irq_unmask(struct irq_data *d)
@@ -501,7 +503,7 @@ static void bcm63xx_external_irq_unmask(
@@ -235,7 +237,7 @@ static void bcm63xx_external_irq_unmask(
spin_unlock_irqrestore(&epic_lock, flags);
if (is_ext_irq_cascaded)

43
target/linux/brcm63xx/patches-3.10/322-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch → target/linux/brcm63xx/patches-3.10/327-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch
View file

@ -1,38 +1,25 @@
From 9e341df1f67c3c64dc5ac668a30bbb6b5ab5f2b4 Mon Sep 17 00:00:00 2001
From 9249f2f6a309e3f45c35d16decdcc5b2cadcadb8 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 12:06:03 +0200
Subject: [PATCH 14/14] MIPS: BCM63XX: allow setting affinity for IPIC
Subject: [PATCH 38/53] MIPS: BCM63XX: allow setting affinity for IPIC
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/bcm63xx/irq.c | 49 +++++++++++++++++++++++++++++++++++++++--------
1 file changed, 41 insertions(+), 8 deletions(-)
arch/mips/bcm63xx/irq.c | 43 +++++++++++++++++++++++++++++++++++++------
1 file changed, 37 insertions(+), 6 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -24,8 +24,10 @@ static void __dispatch_internal_32(int c
static void __dispatch_internal_64(int cpu) __maybe_unused;
static void __internal_irq_mask_32(struct irq_data *d) __maybe_unused;
static void __internal_irq_mask_64(struct irq_data *d) __maybe_unused;
-static void __internal_irq_unmask_32(struct irq_data *d) __maybe_unused;
-static void __internal_irq_unmask_64(struct irq_data *d) __maybe_unused;
+static void __internal_irq_unmask_32(struct irq_data *d,
+ const struct cpumask *mask) __maybe_unused;
+static void __internal_irq_unmask_64(struct irq_data *d,
+ const struct cpumask *mask) __maybe_unused;
static DEFINE_SPINLOCK(ipic_lock);
static DEFINE_SPINLOCK(epic_lock);
@@ -168,7 +170,7 @@ static unsigned int ext_irq_count;
@@ -32,7 +32,7 @@ static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
static void (*internal_irq_mask)(struct irq_data *d);
-static void (*internal_irq_unmask)(struct irq_data *d);
+static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
static void bcm63xx_init_irq(void)
{
@@ -311,6 +313,20 @@ static inline void handle_internal(int i
static inline u32 get_ext_irq_perf_reg(int irq)
@@ -51,6 +51,20 @@ static inline void handle_internal(int i
do_IRQ(intbit + IRQ_INTERNAL_BASE);
}
@ -53,7 +40,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
/*
* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
* prioritize any interrupt relatively to another. the static counter
@@ -381,7 +397,8 @@ static void __internal_irq_mask_##width(
@@ -117,7 +131,8 @@ static void __internal_irq_mask_##width(
spin_unlock_irqrestore(&ipic_lock, flags); \
} \
\
@ -63,16 +50,16 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
{ \
u32 val; \
unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
@@ -398,7 +415,7 @@ static void __internal_irq_unmask_##widt
@@ -132,7 +147,7 @@ static void __internal_irq_unmask_##widt
break; \
\
val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
- if (cpu_online(cpu)) \
+ if (enable_irq_for_cpu(cpu, d, m)) \
val |= (1 << bit); \
else \
val &= ~(1 << bit); \
@@ -455,7 +472,7 @@ static void bcm63xx_internal_irq_mask(st
@@ -189,7 +204,7 @@ static void bcm63xx_internal_irq_mask(st
static void bcm63xx_internal_irq_unmask(struct irq_data *d)
{
@ -81,7 +68,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
}
/*
@@ -503,7 +520,8 @@ static void bcm63xx_external_irq_unmask(
@@ -237,7 +252,8 @@ static void bcm63xx_external_irq_unmask(
spin_unlock_irqrestore(&epic_lock, flags);
if (is_ext_irq_cascaded)
@ -91,7 +78,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
}
static void bcm63xx_external_irq_clear(struct irq_data *d)
@@ -622,6 +640,18 @@ static int bcm63xx_external_irq_set_type
@@ -356,6 +372,18 @@ static int bcm63xx_external_irq_set_type
return IRQ_SET_MASK_OK_NOCOPY;
}
@ -110,7 +97,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
static struct irq_chip bcm63xx_internal_irq_chip = {
.name = "bcm63xx_ipic",
.irq_mask = bcm63xx_internal_irq_mask,
@@ -679,7 +709,10 @@ void __init arch_init_irq(void)
@@ -523,7 +551,10 @@ void __init arch_init_irq(void)
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
#ifdef CONFIG_SMP

0
target/linux/brcm63xx/patches-3.10/323-cfe_simplify_detection.patch → target/linux/brcm63xx/patches-3.10/328-cfe_simplify_detection.patch
View file

0
target/linux/brcm63xx/patches-3.10/324-bcm63xxpart_use_cfedetection.patch → target/linux/brcm63xx/patches-3.10/329-bcm63xxpart_use_cfedetection.patch
View file