04ad02d132
Compared to the "old" driver: - Each device must assign a pinctrl setting to the SPI node to allow the new SPI driver to configure the SPI pins. While here we are also using separate input and output settings so we are independent of whether the bootloader configures the pins correctly. - We use the new "compatible" strings to make the driver choose the correct number of chip-selects for each SoC. - The new driver starts counting the chip-selects at 1 (instead of 0, like the old one did). Thus we have to adjust the devices accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48293
210 lines
4.4 KiB
Text
210 lines
4.4 KiB
Text
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,xway", "lantiq,vr9";
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cpus {
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cpu@0 {
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compatible = "mips,mips34Kc";
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};
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};
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memory@0 {
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device_type = "memory";
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};
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biu@1F800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,biu", "simple-bus";
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reg = <0x1F800000 0x800000>;
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ranges = <0x0 0x1F800000 0x7FFFFF>;
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icu0: icu@80200 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "lantiq,icu";
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reg = <0x80200 0x28
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0x80228 0x28
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0x80250 0x28
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0x80278 0x28
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0x802a0 0x28>;
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};
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watchdog@803F0 {
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compatible = "lantiq,wdt";
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reg = <0x803F0 0x10>;
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};
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};
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sram@1F000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,sram", "simple-bus";
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reg = <0x1F000000 0x800000>;
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ranges = <0x0 0x1F000000 0x7FFFFF>;
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eiu0: eiu@101000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "lantiq,eiu-xway";
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reg = <0x101000 0x1000>;
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interrupt-parent = <&icu0>;
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interrupts = <166 135 66 40 41 42>;
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};
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pmu0: pmu@102000 {
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compatible = "lantiq,pmu-xway";
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reg = <0x102000 0x1000>;
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};
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cgu0: cgu@103000 {
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compatible = "lantiq,cgu-xway";
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reg = <0x103000 0x1000>;
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};
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dcdc@106a00 {
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compatible = "lantiq,dcdc-xrx200";
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reg = <0x106a00 0x200>;
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};
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rcu0: rcu@203000 {
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compatible = "lantiq,rcu-xrx200";
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reg = <0x203000 0x1000>;
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/* irq for thermal sensor */
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interrupt-parent = <&icu0>;
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interrupts = <115>;
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};
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xbar0: xbar@400000 {
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compatible = "lantiq,xbar-xway";
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reg = <0x400000 0x1000>;
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};
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};
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fpi@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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ranges = <0x0 0x10000000 0xEEFFFFF>;
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reg = <0x10000000 0xEF00000>;
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
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1 0 0x4000000 0x4000010>; /* addsel1 */
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compatible = "lantiq,localbus", "simple-bus";
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};
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gptu@E100A00 {
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compatible = "lantiq,gptu-xway";
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reg = <0xE100A00 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <126 127 128 129 130 131>;
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};
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asc0: serial@E100400 {
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compatible = "lantiq,asc";
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reg = <0xE100400 0x400>;
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interrupt-parent = <&icu0>;
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interrupts = <104 105 106>;
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status = "disabled";
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};
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spi: spi@E100800 {
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compatible = "lantiq,xrx200-spi";
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reg = <0xE100800 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <22 23 24>;
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interrupt-names = "spi_rx", "spi_tx", "spi_err",
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"spi_frm";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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gpio: pinmux@E100B10 {
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compatible = "lantiq,xrx200-pinctrl";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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};
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asc1: serial@E100C00 {
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compatible = "lantiq,asc";
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reg = <0xE100C00 0x400>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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};
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deu@E103100 {
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compatible = "lantiq,deu-xrx200";
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reg = <0xE103100 0xf00>;
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};
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dma0: dma@E104100 {
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compatible = "lantiq,dma-xway";
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reg = <0xE104100 0x800>;
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};
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ebu0: ebu@E105300 {
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compatible = "lantiq,ebu-xway";
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reg = <0xE105300 0x100>;
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};
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ifxhcd@E101000 {
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status = "disabled";
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compatible = "lantiq,ifxhcd-xrx200", "lantiq,ifxhcd-xrx200-dwc2";
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reg = <0xE101000 0x1000
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0xE120000 0x3f000>;
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interrupt-parent = <&icu0>;
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interrupts = <62 91>;
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};
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ifxhcd@E106000 {
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status = "disabled";
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compatible = "lantiq,ifxhcd-xrx200-dwc2";
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reg = <0xE106000 0x1000>;
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interrupt-parent = <&icu0>;
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interrupts = <91>;
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};
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mei@E116000 {
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compatible = "lantiq,mei-xrx200";
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reg = <0xE116000 0x9c>;
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interrupt-parent = <&icu0>;
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interrupts = <63>;
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};
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ppe@E234000 {
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compatible = "lantiq,ppe-xrx200";
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interrupt-parent = <&icu0>;
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interrupts = <96>;
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};
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pcie@d900000 {
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interrupt-parent = <&icu0>;
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interrupts = <161 144>;
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compatible = "lantiq,pcie-xrx200";
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gpio-reset = <&gpio 38 0>;
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};
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pci0: pci@E105400 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "lantiq,pci-xway";
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bus-range = <0x0 0x0>;
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ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
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0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
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reg = <0x7000000 0x8000 /* config space */
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0xE105400 0x400>; /* pci bridge */
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status = "disabled";
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};
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};
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vdsl {
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compatible = "lantiq,vdsl-vrx200";
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};
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};
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