It seems that the PCI controller does not support I/O ports, so remove
the ports range. Also correct the beginning of the memory range and its
size.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42503
Use __raw_{read,write}l accessors and use Abort interrupt to detect a
configuration space read/write errors. The second change improves errors
detection, what improves the device presence detection and helps us to
avoid following (and similar) errors:
pci 0000:00:00.2: ignoring class 0x7e0200 (doesn't match header type 02)
pci 0000:00:00.2: bridge configuration invalid ([bus 03-90]), reconfiguring
pci 0000:00:00.2: not setting up bridge for bus 0000:01
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42502
Add PCI IRQ controller to facilitate interrupt handling, move interrupts
initialization to the IRQ controller initialization from
pcibios_plat_dev_init() callback.
Also remove odd PCI dev configuration manipulation from pcibios_plat_dev_init()
callback.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42501
Explicitly configure PCI host controller, and do not expose it to PCI
subsystem. The PCI host controller acts as a usual PCI device connected
to the bus, but its configuration as a usual PCI device is senseless,
since the host controller provide access to _internal_ memory space for
_external_ device.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42500
- add comment, which briefly describes PCI controller features and
Fonera 2.0g schematics.
- rename several functions and structures, to make it clear that this
code only for AR2315 chips.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42499
Caller (generic PCI code) already do proper locking so no need to add
another one here.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42498
Remove options which already selected by ATHEROS_AR231X on which
ATHEROS_AR2315 depends.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42497
- remove odd flags and branching
- add __init mark
- make shorter variables names
- returns true or false from boolean functions
- unwrap short function declarations
- unwrap quoted string
- rename macroses with names in CamelCase
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42495
- use ether_foo() routines to work with addresses
- use ETH_ALEN inplace of magic '6'
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42494
Use mutex inplace of spinlock to make code simple, also call
mutex_{lock,unlock} explicitly to avoid sparse warning about context
imbalance.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42491
Remove FSF mailing address as suggested by checkpach and place license
URL.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42487
Missing this headers cause several sparse "symbol 'foo' was not
declared. Should it be static?" warnings.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 42483
This switches to kernel 3.10 that was prepared by Hauke in r41531 :
gemini: add support for kernel 3.10
This is compile tested only, please run test and report back.
I've simply checked if it still compiles, unfortunately we didn't get
any feedback for this target.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 42450
the old dwc_otg driver is starting to fall apart and fails on newer 3g
modems and some storage devices. switch to the upstream dwc2 driver which
is no longer in staging/.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 42446
While the AR9331 has a gigabit MAC towards the internal switch, the
integrated PHYs however are only 100-base-tx capable. The existing code
however advertieses gigabit capability in the link status word. If you
attach such a PHY to a gigabit capable switch on the remote end, with
some probability it attempts to negotiate gigabit and fails, falling
baco to the AR9331 assuming a 10mbit half-duplex link. This has been
observed quite frequently with the Carambola2 and gigabit capable
switches.
In ath79_register_eth(), "pdata->has_gbit = 1;" is set unconditionally
for both AR9331 ethernet ports. This is most likely wrong. Despite the
two MAC IP cores being gigabit MACs, the MAC for eth1 is connected to a
100base-T PHY via MII. The has_gbit attribute is used in the ethernet
driver to determine the supported link modes.
So either pdata->has_gbit is not set to 1 anymore, or the ethernet
driver needs to be modified to determine the advertised link code word
on another criteria than pdata->has_gbit. This patch implements the
former solution.
Signed-off-by: Harald Welte <laforge@gnumonks.org>
SVN-Revision: 42432
