Eth0 is attached to mac0 of the switch with a fixed link and and not to
phy4 in single phy mode, so configuring it to anything but 1000FD will
break the connection, which will happen if a only 100 Mbit capapble device
is plugged into the wan port.
Fix this by not taking the state from phy4 and just configuring a fixed link
for eth0.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 47695
*Enable SMEM MTD parser and its dependencies (SMEM & HW spinlocks) in
the kernel config
*Replaces the MTD layout in DT by the dynamic layout provided by the
SMEM parser for AP148
Using the OF based parser is still possible on platforms which have a
fixed MTD partition layout.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46658
This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field
We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46655
Previous patch 6f2905eeb6ce5ddec8d12d677e1f377a940b537b enabled ADM in
the kernel, which causes a kernel panic when accessing the SPI flash.
As a workaround, We'll disable DMA for the flash for now. It was not
enabled previously anyway so we'll just leave it as is.
Reported-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46587
These patches add support for ipq806x NAND flash controller. Most of
these are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/8/3/16
This patch just modifies the kernel code, but doesn't change the config.
It should be harmless.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46568
These are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/3/17/19
They are enabled on both 3.18 and 4.1 kernel. Patches 150 to 154 are
applying changes merged since 3.18; they enable mechanisms used by the
ADM driver.
ADM engine is used by the NAND controller, so it is necessary to
bring-up NAND flash support.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46567
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but
the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing
the pinmux numbering to match the controller's one.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46556
This driver has been cherry-picked and backported from the following
LKML thread:
*https://lkml.org/lkml/2015/5/26/744
It also updates the DT accordingly.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 45831
