ipq806x: fix pcie pinmux naming in ipq806x dts
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing the pinmux numbering to match the controller's one. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46556
This commit is contained in:
parent
c4c986e419
commit
f7651fdba5
6 changed files with 40 additions and 49 deletions
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@ -15,11 +15,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -30,6 +30,22 @@
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@@ -35,6 +35,22 @@
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bias-disable;
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};
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+ pcie1_pins: pcie1_pinmux {
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ drive-strength = <2>;
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@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ drive-strength = <2>;
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@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -133,5 +149,19 @@
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@@ -138,5 +154,19 @@
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usb30@1 {
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status = "ok";
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};
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@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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bias-disable;
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};
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+ pcie1_pins: pcie1_pinmux {
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ drive-strength = <2>;
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@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ drive-strength = <2>;
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@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie3_pins: pcie3_pinmux {
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+ pcie2_pins: pcie2_pinmux {
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+ mux {
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+ pins = "gpio63";
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+ drive-strength = <2>;
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@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 63 0>;
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+ pinctrl-0 = <&pcie3_pins>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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@ -259,10 +259,3 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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hs_phy_1: phy@100f8800 {
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compatible = "qcom,dwc3-hs-usb-phy";
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reg = <0x100f8800 0x30>;
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@@ -389,6 +514,5 @@
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dr_mode = "host";
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};
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};
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-
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};
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};
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@ -11,7 +11,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -14,8 +14,9 @@
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@@ -19,8 +19,9 @@
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};
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};
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@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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chosen {
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@@ -54,6 +55,15 @@
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@@ -59,6 +60,15 @@
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bias-none;
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};
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};
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@ -38,8 +38,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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gsbi@16300000 {
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@@ -163,5 +173,33 @@
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pinctrl-0 = <&pcie2_pins>;
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@@ -168,5 +178,33 @@
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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};
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+
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@ -99,7 +99,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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gsbi2: gsbi@12480000 {
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@@ -173,5 +183,44 @@
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pinctrl-0 = <&pcie3_pins>;
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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};
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+
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@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -64,6 +64,16 @@
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@@ -71,6 +71,16 @@
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bias-disable;
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};
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};
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@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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gsbi@16300000 {
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@@ -201,5 +211,26 @@
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@@ -208,5 +218,26 @@
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reg = <4>;
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};
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};
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@ -58,7 +58,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -72,6 +72,14 @@
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@@ -75,6 +75,14 @@
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bias-disable;
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};
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};
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@ -73,7 +73,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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gsbi2: gsbi@12480000 {
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@@ -222,5 +230,40 @@
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@@ -225,5 +233,40 @@
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reg = <7>;
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};
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};
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@ -116,11 +116,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -638,5 +638,91 @@
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dr_mode = "host";
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@@ -657,5 +657,90 @@
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};
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};
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+
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+ nss_common: syscon@03000000 {
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+ compatible = "syscon";
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+ reg = <0x03000000 0x0000FFFF>;
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@ -19,7 +19,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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bias-disable;
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};
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+ pcie1_pins: pcie1_pinmux {
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ drive-strength = <2>;
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@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ drive-strength = <2>;
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@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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bias-disable;
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};
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+ pcie1_pins: pcie1_pinmux {
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ drive-strength = <2>;
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@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ drive-strength = <2>;
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@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ };
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+ };
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+
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+ pcie3_pins: pcie3_pinmux {
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+ pcie2_pins: pcie2_pinmux {
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+ mux {
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+ pins = "gpio63";
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+ drive-strength = <2>;
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@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 63 0>;
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+ pinctrl-0 = <&pcie3_pins>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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@ -125,11 +125,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <include/dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -329,5 +331,128 @@
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@@ -329,5 +331,127 @@
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#reset-cells = <1>;
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};
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@ -255,6 +255,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+
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+ status = "disabled";
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+ };
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+
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};
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};
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@ -39,7 +39,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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gsbi@16300000 {
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@@ -144,5 +154,33 @@
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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};
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+
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@ -99,7 +99,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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gsbi2: gsbi@12480000 {
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@@ -173,5 +183,44 @@
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pinctrl-0 = <&pcie3_pins>;
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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};
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+
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@ -116,10 +116,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -578,5 +578,91 @@
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@@ -577,5 +577,91 @@
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status = "disabled";
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};
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+
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+ nss_common: syscon@03000000 {
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+ compatible = "syscon";
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+ reg = <0x03000000 0x0000FFFF>;
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@ -205,6 +206,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+
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+ status = "disabled";
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+ };
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+
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};
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};
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