Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
Resolves an issue where isochronouse USB would cause the driver to hang as
well as scheduling issues.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33579
For cns3xxx SCU_CONFIGURATION always shows multipe cores but SCU_CPU_STATUS
shows which ones are active.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33566
Increase the size of the buffer used for eeprom reads during the platform configuration of the Gateworks laguna. The model name read in is 16 bytes but the original buffer was only 8 bytes.
Signed-off-by: David Acker <dacker@rajant.com>
SVN-Revision: 32833
