similar to what was observed on kirkwood this significantly accelerates
btrfs write operations.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43498
gpio-beeper module was added to the kernel recently.
Make use of it to drive the piezoelectric buzzer of the kd20.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43496
This is a swconfig driver for the Marvell 88E6171 switch,
which is a 7-port GigE switch with two CPU ports and 64
802.1q VLANs.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43486
Factor out set_mirror_regs to ar8xxx_chip.
Remove related chip_is_... checks.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43468
Factor out info whether switch should be configured at probe stage
to ar8xxx_chip. Remove related chip_is_... checks.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43466
Patch to add the buildprofile for the GL-Init-6408A-v1 and the GL-Inet-6416A-v1
Both devices are identical, only difference is one comes with 8MB flash and
the other with 16MB flash
Official website: http://www.gl-inet.com/w/?page_id=241&lang=en
Comprehensive list of specs: https://revspace.nl/GL-Inet
Signed-off-by: Martijn Zilverschoon <martijn@friedzombie.com>
SVN-Revision: 43462
Add the required nodes for the interrupt controllers and register
them through DT when a DTB is present.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43457
Add irq-domain aware irqchip drivers for the irq controllers of bcm63xx
and switch to use them.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43454
At least on my Iomega ix2-200 system, this makes btrfs writes about 30% faster.
Signed-off-by: Richard Kunze <richard.kunze@web.de>
SVN-Revision: 43434
This patch introduces some code that is compiled in whenever
CONFIG_BRIDGE_NETFILTER is built, with the code called from code compiled under
CONFIG_BRIDGE, CONFIG_BRIDGE_IGMP_SNOOPING or CONFIG_BRIDGE_NF_EBTABLES.
Unfortunately, these options aren't setting explicitly the dependency they now
have on CONFIG_BRIDGE_NETFILTER, for obvious reasons for CONFIG_BRIDGE.
However, this is not working really well when CONFIG_BRIDGE_NETFILTER is built
as a module, since code statically compiled will now use a function that is not
in the kernel image, which makes the linker grumpy.
Solve this by removing the option to build CONFIG_BRIDGE_NETFILTER as a module,
and protect our function definition by an IS_BUILTIN instead of a IS_ENABLED
macro. This fixes the issue for CONFIG_BRIDGE and CONFIG_BRIDGE_IGMP_SNOOPING.
Fixing CONFIG_BRIDGE_NF_EBTABLES has to be handled a bit differently, since it
directly references a variable that will not be declared if
CONFIG_BRIDGE_NETFILTER is not set. Protect the variable affectations by an
ifdef to make sure this doesn't happen.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 43419
This is the oxnas target previously developed at
http://gitorious.org/openwrt-oxnas
Basically, this consolidates the changes and addtionas from
http://github.org/kref/linux-oxnas
into a new OpenWrt hardware target 'oxnas' adding support for
PLX Technology NAS7820/NAS7821/NAS7825/...
formally known as
Oxford Semiconductor OXE810SE/OXE815/OX820/...
For now there are 4 supported boards:
Cloud Engines Pogoplug V3 (without PCIe)
fully supported
Cloud Engines Pogoplug Pro (with PCIe)
fully supported
MitraStar STG-212
aka ZyXEL NSA-212,
aka Medion Akoya P89625 / P89636 / P89626 / P89630,
aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587
fully supported, see http://wiki.openwrt.org/toh/medion/md86587
Shuttle KD-20
partially supported (S-ATA driver lacks support for 2nd port)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43388
This adds support for the TP-LINK CPE210/220/510/520 (Pharos series). These
devices are very similar to the Ubiquiti NanoStations, but with better specs:
faster CPU, more RAM, 2x2 MIMO.
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
SVN-Revision: 43385
With kernel 3.14 dts target p1010rdb was renamed to p1010rdb-pa.
To maintain compatibility define p1010rdb-pa as new standard and
copy p1010rdb.dts to p1010rdb-pa.dts under 3.10.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43371
If there is no board support in the kernel, it does not make sense to
build images for devices. So drop any images for board ids for which
there are nc corresponding board_info structs in the kernel.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43364
Patch reverts 43332 which seems to cause issues with VLAN functionality.
Add a specific check to check whether ANEG is still enabled and re-enable
it if necessary. Disable generic phy soft reset for kernel >=3.16.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43356
This target can be emulated using ARM's Foundation_V8 simulator
software or qemu-system-aarch64 using the command-line described in the
README file.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 43355
Move compatible strings from board structs into separate table. This
allows for several board compatibles to match to the same board in case
e.g. only the flash size / partitions differ.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43341
We should make sure that also for ar8216 hw gets initialized.
For ar8216 hw_init is a dummy currently. The hw_init used for ar8236
should be generic enough to be usable with ar8216 too.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43334
Move the PHY fixup call to the PHY init loop.
Use ar8xxx_has_gige in the PHY init instead of passing the gigE
capability via function parameter.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43333
Kernel 3.14 introduced a switch reset in phy_init_hw in drivers/net/phy
causing BMCR_ANENABLE to get cleared.
Due to the fact that ar8xxx_phy_config_aneg does nothing for
PHY 0 autonegatiation support remains disabled.
This can cause ports to operate at 10MBit/half-duplex only.
Fix this by calling genphy_config_aneg for PHY 0 too as
genphy_config_aneg sets BMCR_ANENABLE if it's not yet set.
Fixes: ticket 17800
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43332
PHY init code in the switch-specific hw_init functions is mainly
identical. Factor it out into a generic ar8xxx_phy_init function.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 43331
Move phy fixup code from the chip-specific hw_init functions into a
fixup_phys callback.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43330
Currently there is a fixed 1000ms wait time after the switch was reset.
Most if not all switches need much less time to perform a reset.
Therefore replace the fixed wait time with polling for BMCR_RESET to
be cleared.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 43329
