Initial idea was to use package with this PHY driver for devices that
need it. Unfortunately this can't work as bgmac is built-in and PHY
probing happens before loading modules - it results in PHY subsystem
picking default (generic) PHY driver.
There were two ways of solving this:
1) Making bcm53xx use bgmac as module
xor
2) Built-in Broadcom PHY driver
After some quick discussion it seems we can simply built-in the driver
as increased kenel size is relatively small (1805 B).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
There are many targets using user space scripts to generate firmware but
bcm53xx doesn't need this, so let's disable that kernel option.
This lets us avoid some scary-looking kernel warnings like:
brcmfmac 0001:04:00.0: Falling back to user helper
firmware brcm!brcmfmac43602-pcie.txt: firmware_loading_store: map pages failed
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This reverts commit b3be33f135.
CFE is known to fail in some non-standard cases, e.g. when using kernel
or format different that what was tested by Broadcom. This kernel change
triggered some problem with booting OpenWrt kernel stored in Seama.
As long as Seama checksum was covering enough data, it was working fine.
We need to change it however, because calculating MD5 over part of UBI
containing SquashFS is unsafe. UBI may move PEBs depending on flash
wearing level which would break CFE booting the image.
For some reason this kernel change was breaking CFE. Calculating MD5
over 0x47ffc0 B data or less (there is 0x40 B long header) was stopping
booting process at:
Starting program at 0x00008000
As our kernel is usually 0x3fffc0 B it was affected by this problem.
Reverting this change fixes sysupgrade (which already uses kernel size
for MD5 calculation) and will allow us to adjust "fixseama" command call
on the first boot.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
In kernel 4.7 there is upstreamed b53 driver using (mostly?) the same
symbols as our b53 does. Change our symbols so both drivers can coexist
in kernel tree.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jonas.gorski@gmail.com>
For some time now m25p80 supports 32 MiB flashes and we just needed to
patch spi-nor to support JEDEC incompatible w25q128. Also by switching
to m25p80 we gain accelerated SPI flash reads.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 49260
