Commit graph

11 commits

Author SHA1 Message Date
Jonas Gorski
e9390dcf23 ipq806x: ap148/r7500: fix eth0 for non gige speeds
Eth0 is attached to mac0 of the switch with a fixed link and and not to
phy4 in single phy mode, so configuring it to anything but 1000FD will
break the connection, which will happen if a only 100 Mbit capapble device
is plugged into the wan port.

Fix this by not taking the state from phy4 and just configuring a fixed link
for eth0.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 47695
2015-12-02 22:16:23 +00:00
Felix Fietkau
49d4a980d7 ipq806x: fix pcie reset gpio definions and move them to the common .dtsi file
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47544
2015-11-21 10:54:58 +00:00
Felix Fietkau
575413a779 ipq806x: fix pcie tx0-term-offset setting
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47543
2015-11-21 10:54:53 +00:00
Jonas Gorski
9f44a347ea ipq806x: enable smem-parser for nand on AP148
Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 46785
2015-09-04 14:44:36 +00:00
John Crispin
b0b59a8e75 ipq806x: switch AP148 to using SMEM based MTD parser
*Enable SMEM MTD parser and its dependencies (SMEM & HW spinlocks) in
 the kernel config
*Replaces the MTD layout in DT by the dynamic layout provided by the
 SMEM parser for AP148

Using the OF based parser is still possible on platforms which have a
fixed MTD partition layout.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46658
2015-08-17 06:18:15 +00:00
John Crispin
6b775f4517 ipq806x: add hwspinlock support
This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field

We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46655
2015-08-17 06:17:47 +00:00
Felix Fietkau
6cc5919e8a ipq806x: disable DMA on the SPI flash
Previous patch 6f2905eeb6ce5ddec8d12d677e1f377a940b537b enabled ADM in
the kernel, which causes a kernel panic when accessing the SPI flash.

As a workaround, We'll disable DMA for the flash for now. It was not
enabled previously anyway so we'll just leave it as is.

Reported-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46587
2015-08-13 19:02:16 +00:00
Felix Fietkau
d523866eb3 ipq806x: add NAND flash controller support
These patches add support for ipq806x NAND flash controller. Most of
these are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/8/3/16

This patch just modifies the kernel code, but doesn't change the config.
It should be harmless.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46568
2015-08-07 08:36:31 +00:00
Felix Fietkau
c7bf2accc9 ipq806x: Add ADM support
These are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/3/17/19

They are enabled on both 3.18 and 4.1 kernel. Patches 150 to 154 are
applying changes merged since 3.18; they enable mechanisms used by the
ADM driver.

ADM engine is used by the NAND controller, so it is necessary to
bring-up NAND flash support.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46567
2015-08-07 08:36:16 +00:00
Felix Fietkau
f7651fdba5 ipq806x: fix pcie pinmux naming in ipq806x dts
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but
the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing
the pinmux numbering to match the controller's one.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46556
2015-08-04 23:09:55 +00:00
John Crispin
d2a2eb7e48 ipq806x: replace caf nss-gmac driver by upstream stmmac
This driver has been cherry-picked and backported from the following
LKML thread:
*https://lkml.org/lkml/2015/5/26/744

It also updates the DT accordingly.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 45831
2015-05-29 12:26:01 +00:00