ar71xx: add NAND driver for the Mikrotik RB91x boards
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39097
This commit is contained in:
Gabor Juhos
parent
d7a0184446
commit
8461ffccc1
2 changed files with 378 additions and 0 deletions
355
target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c
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355
target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c
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/*
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* NAND flash driver for the MikroTik RouterBOARD 91x series
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*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#define DRV_NAME "rb91x-nand"
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#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
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#define RB91X_NAND_NRE_ENABLE BIT(3)
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#define RB91X_NAND_RDY BIT(4)
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#define RB91X_LATCH_ENABLE BIT(11)
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#define RB91X_NAND_NRWE BIT(12)
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#define RB91X_NAND_NCE BIT(13)
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#define RB91X_NAND_CLE BIT(14)
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#define RB91X_NAND_ALE BIT(15)
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#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
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BIT(13) | BIT(14) | BIT(15))
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#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
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#define RB91X_NAND_OUTPUT_BITS \
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(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
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#define RB91X_NAND_LOW_DATA_MASK 0x1f
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#define RB91X_NAND_HIGH_DATA_MASK 0xe0
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#define RB91X_NAND_HIGH_DATA_SHIFT 8
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struct rb91x_nand_info {
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struct nand_chip chip;
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struct mtd_info mtd;
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};
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static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
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{
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return container_of(mtd, struct rb91x_nand_info, mtd);
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}
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/*
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* We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
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* will not be able to find the kernel that we load.
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*/
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static struct nand_ecclayout rb91x_nand_ecclayout = {
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.eccbytes = 6,
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.eccpos = { 8, 9, 10, 13, 14, 15 },
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.oobavail = 9,
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.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
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};
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static struct mtd_partition rb91x_nand_partitions[] = {
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{
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.name = "booter",
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.offset = 0,
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.size = (256 * 1024),
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = (256 * 1024),
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.size = (4 * 1024 * 1024) - (256 * 1024),
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}, {
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.name = "rootfs",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static void rb91x_change_gpo(u32 clear, u32 set)
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{
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void __iomem *base = ath79_gpio_base;
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static unsigned on = 0xE002800;
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static unsigned off = 0x0000C008;
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static unsigned oe = 0;
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static DEFINE_SPINLOCK(lock);
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unsigned long flags;
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spin_lock_irqsave(&lock, flags);
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on = (on | set) & ~clear;
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off = (off | clear) & ~set;
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if (!oe)
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oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
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if (on & RB91X_LATCH_ENABLE) {
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u32 t;
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t = oe & __raw_readl(base + AR71XX_GPIO_REG_OE);
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t &= ~(on | off);
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__raw_writel(t, base + AR71XX_GPIO_REG_OE);
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__raw_writel(off, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(on, base + AR71XX_GPIO_REG_SET);
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} else if (clear & RB91X_LATCH_ENABLE) {
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oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
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__raw_writel(RB91X_LATCH_ENABLE,
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base + AR71XX_GPIO_REG_CLEAR);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
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}
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spin_unlock_irqrestore(&lock, flags);
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}
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static inline void rb91x_latch_enable(void)
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{
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rb91x_change_gpo(RB91X_LATCH_ENABLE, 0);
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}
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static inline void rb91x_latch_disable(void)
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{
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rb91x_change_gpo(0, RB91X_LATCH_ENABLE);
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}
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static void rb91x_nand_write(const u8 *buf, unsigned len)
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{
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void __iomem *base = ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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u32 out;
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unsigned i;
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rb91x_latch_enable();
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* set data lines to output mode */
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__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
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base + AR71XX_GPIO_REG_OE);
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out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
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for (i = 0; i != len; i++) {
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u32 data;
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data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
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RB91X_NAND_HIGH_DATA_SHIFT;
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data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
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data |= out;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* deactivate WE line */
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data |= RB91X_NAND_NRWE;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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}
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/* restore registers */
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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rb91x_latch_disable();
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}
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static void rb91x_nand_read(u8 *read_buf, unsigned len)
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{
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void __iomem *base = ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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unsigned i;
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/* save registers */
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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/* select nRE mode */
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rb91x_change_gpo(0, RB91X_NAND_NRE_ENABLE);
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/* enable latch */
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rb91x_latch_enable();
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* set data lines to input mode */
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__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
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base + AR71XX_GPIO_REG_OE);
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for (i = 0; i < len; i++) {
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u32 in;
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u8 data;
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/* activate RE line */
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__raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
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/* read input lines */
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in = __raw_readl(base + AR71XX_GPIO_REG_IN);
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/* deactivate RE line */
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__raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
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data = (in & RB91X_NAND_LOW_DATA_MASK);
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data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
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RB91X_NAND_HIGH_DATA_MASK;
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read_buf[i] = data;
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}
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/* restore registers */
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* disable latch */
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rb91x_latch_disable();
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/* deselect nRE mode */
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rb91x_change_gpo(RB91X_NAND_NRE_ENABLE, 0);
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}
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static int rb91x_nand_dev_ready(struct mtd_info *mtd)
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{
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void __iomem *base = ath79_gpio_base;
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return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB91X_NAND_RDY);
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}
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static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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u32 on = 0;
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u32 off;
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if (!(ctrl & NAND_NCE))
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on |= RB91X_NAND_NCE;
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if (ctrl & NAND_CLE)
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on |= RB91X_NAND_CLE;
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if (ctrl & NAND_ALE)
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on |= RB91X_NAND_ALE;
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off = on ^ (RB91X_NAND_ALE | RB91X_NAND_NCE | RB91X_NAND_CLE);
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rb91x_change_gpo(off, on);
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}
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if (cmd != NAND_CMD_NONE) {
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u8 t = cmd;
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rb91x_nand_write(&t, 1);
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}
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}
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static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
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{
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u8 data = 0xff;
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rb91x_nand_read(&data, 1);
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return data;
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}
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static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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rb91x_nand_read(buf, len);
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}
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static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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rb91x_nand_write(buf, len);
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}
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static int rb91x_nand_probe(struct platform_device *pdev)
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{
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struct rb91x_nand_info *info;
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int ret;
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pr_info(DRV_DESC "\n");
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info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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info->chip.priv = &info;
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info->mtd.priv = &info->chip;
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info->mtd.owner = THIS_MODULE;
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info->chip.cmd_ctrl = rb91x_nand_cmd_ctrl;
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info->chip.dev_ready = rb91x_nand_dev_ready;
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info->chip.read_byte = rb91x_nand_read_byte;
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info->chip.write_buf = rb91x_nand_write_buf;
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info->chip.read_buf = rb91x_nand_read_buf;
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info->chip.chip_delay = 25;
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info->chip.ecc.mode = NAND_ECC_SOFT;
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platform_set_drvdata(pdev, info);
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ret = nand_scan_ident(&info->mtd, 1, NULL);
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if (ret)
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return ret;
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if (info->mtd.writesize == 512)
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info->chip.ecc.layout = &rb91x_nand_ecclayout;
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ret = nand_scan_tail(&info->mtd);
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if (ret)
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return ret;
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ret = mtd_device_register(&info->mtd, rb91x_nand_partitions,
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ARRAY_SIZE(rb91x_nand_partitions));
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if (ret)
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goto err_release_nand;
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return 0;
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err_release_nand:
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nand_release(&info->mtd);
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return ret;
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}
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static int rb91x_nand_remove(struct platform_device *pdev)
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{
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struct rb91x_nand_info *info = platform_get_drvdata(pdev);
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nand_release(&info->mtd);
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return 0;
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}
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static struct platform_driver rb91x_nand_driver = {
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.probe = rb91x_nand_probe,
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.remove = rb91x_nand_remove,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(rb91x_nand_driver);
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MODULE_DESCRIPTION(DRV_DESC);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,23 @@
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -552,6 +552,10 @@ config MTD_NAND_RB750
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tristate "NAND flash driver for the RouterBoard 750"
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depends on MTD_NAND && ATH79_MACH_RB750
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+config MTD_NAND_RB91X
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+ tristate "NAND flash driver for the RouterBOARD 91x series"
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+ depends on MTD_NAND && ATH79_MACH_RB91X
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+
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config MTD_NAND_AR934X
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tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
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depends on (SOC_AR934X || SOC_QCA955X)
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nan
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obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
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obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
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obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
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+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
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obj-$(CONFIG_MTD_ALAUDA) += alauda.o
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obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
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obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
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