brcm63xx: add support for chip variants
Some SoCs have variants which are mostly the same, but use a different chip id (or not). Add code for detecting them and handling them as their standard counterparts. This adds support for e.g. BCM6369. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39269
This commit is contained in:
Jonas Gorski
parent
db36359f48
commit
76164e1a36
8 changed files with 258 additions and 4 deletions
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@ -0,0 +1,77 @@
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From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:08:36 +0100
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Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper
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---
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arch/mips/bcm63xx/cpu.c | 10 ++++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++
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2 files changed, 28 insertions(+)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs);
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u16 bcm63xx_cpu_id __read_mostly;
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EXPORT_SYMBOL(bcm63xx_cpu_id);
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+static u32 bcm63xx_cpu_variant __read_mostly;
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+
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static u8 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = {
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};
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+u32 bcm63xx_get_cpu_variant(void)
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+{
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+ return bcm63xx_cpu_variant;
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+}
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+
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+EXPORT_SYMBOL(bcm63xx_get_cpu_variant);
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+
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u8 bcm63xx_get_cpu_rev(void)
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{
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return bcm63xx_cpu_rev;
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@@ -332,6 +341,7 @@ void __init bcm63xx_cpu_init(void)
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/* read out CPU type */
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tmp = bcm_readl(chipid_reg);
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bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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+ bcm63xx_cpu_variant = bcm63xx_cpu_id;
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bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
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switch (bcm63xx_cpu_id) {
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -19,6 +19,7 @@
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#define BCM6368_CPU_ID 0x6368
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void __init bcm63xx_cpu_init(void);
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+u32 bcm63xx_get_cpu_variant(void);
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u8 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu
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#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
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#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
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+#define BCMCPU_VARIANT_IS_3368() \
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+ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6328() \
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+ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6338() \
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+ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6345() \
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+ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6348() \
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+ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6358() \
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+ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6362() \
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+ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6368() \
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+ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
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+
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/*
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* While registers sets are (mostly) the same across 63xx CPU, base
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* address of these sets do change.
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@ -0,0 +1,20 @@
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From 9cd8b4a2ee9d0e6a5b91845bdd6f4b7e114fc8c4 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:22:41 +0100
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Subject: [PATCH 41/53] MIPS: BCM63XX: define variant id field
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++
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1 file changed, 2 insertions(+)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -9,6 +9,8 @@
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#define PERF_REV_REG 0x0
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#define REV_CHIPID_SHIFT 16
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#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
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+#define REV_VARID_SHIFT 8
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+#define REV_VARID_MASK (0xf << REV_VARID_SHIFT)
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#define REV_REVID_SHIFT 0
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#define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
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@ -0,0 +1,67 @@
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From 6c8d94aaf5e2f0a3327e4f69ccd980bd5617f925 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:30:59 +0100
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Subject: [PATCH 42/53] MIPS: BCM63XX: detect bcm6328 variants
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---
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arch/mips/bcm63xx/cpu.c | 10 ++++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++--
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2 files changed, 16 insertions(+), 2 deletions(-)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -304,6 +304,7 @@ void __init bcm63xx_cpu_init(void)
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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u32 chipid_reg;
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+ u8 varid;
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/* soc registers location depends on cpu type */
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chipid_reg = 0;
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@@ -343,6 +344,7 @@ void __init bcm63xx_cpu_init(void)
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bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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bcm63xx_cpu_variant = bcm63xx_cpu_id;
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bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
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+ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
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switch (bcm63xx_cpu_id) {
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case BCM3368_CPU_ID:
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@@ -352,6 +354,14 @@ void __init bcm63xx_cpu_init(void)
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case BCM6328_CPU_ID:
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bcm63xx_regs_base = bcm6328_regs_base;
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bcm63xx_irqs = bcm6328_irqs;
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+
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+ if (varid == 1)
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+ bcm63xx_cpu_variant = BCM63281_CPU_ID;
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+ else if (varid == 3)
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+ bcm63xx_cpu_variant = BCM63283_CPU_ID;
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+ else
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+ pr_warn("unknown BCM6328 variant: %x\n", varid);
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+
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break;
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case BCM6338_CPU_ID:
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bcm63xx_regs_base = bcm6338_regs_base;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -11,6 +11,8 @@
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*/
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#define BCM3368_CPU_ID 0x3368
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#define BCM6328_CPU_ID 0x6328
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+#define BCM63281_CPU_ID 0x63281
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+#define BCM63283_CPU_ID 0x63283
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu
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#define BCMCPU_VARIANT_IS_3368() \
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(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
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-#define BCMCPU_VARIANT_IS_6328() \
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- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
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+#define BCMCPU_VARIANT_IS_63281() \
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+ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)
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+#define BCMCPU_VARIANT_IS_63283() \
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+ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID)
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#define BCMCPU_VARIANT_IS_6338() \
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(bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
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#define BCMCPU_VARIANT_IS_6345() \
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@ -0,0 +1,46 @@
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From dc48adb13a99086d1f484d3379a918626c5b1658 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:33:28 +0100
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Subject: [PATCH 43/53] MIPS: BCM63XX: detect BCM6362 variants
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---
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arch/mips/bcm63xx/cpu.c | 8 ++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++
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2 files changed, 11 insertions(+)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -382,6 +382,14 @@ void __init bcm63xx_cpu_init(void)
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case BCM6362_CPU_ID:
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bcm63xx_regs_base = bcm6362_regs_base;
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bcm63xx_irqs = bcm6362_irqs;
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+
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+ if (varid == 1)
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+ bcm63xx_cpu_variant = BCM6362_CPU_ID;
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+ else if (varid == 2)
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+ bcm63xx_cpu_variant = BCM6361_CPU_ID;
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+ else
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+ pr_warn("unknown BCM6362 variant: %x\n", varid);
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+
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break;
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case BCM6368_CPU_ID:
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bcm63xx_regs_base = bcm6368_regs_base;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -17,6 +17,7 @@
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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+#define BCM6361_CPU_ID 0x6361
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#define BCM6362_CPU_ID 0x6362
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#define BCM6368_CPU_ID 0x6368
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@@ -99,6 +100,8 @@ static inline u16 __pure bcm63xx_get_cpu
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(bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
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#define BCMCPU_VARIANT_IS_6358() \
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(bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6361() \
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+ (bcm63xx_get_cpu_variant() == BCM6361_CPU_ID)
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#define BCMCPU_VARIANT_IS_6362() \
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(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
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#define BCMCPU_VARIANT_IS_6368() \
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@ -0,0 +1,44 @@
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From 311b0246d51e09d13464e76abb0e231c855dd333 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 7 Dec 2013 14:36:56 +0100
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Subject: [PATCH 44/53] MIPS: BCM63XX: add support for BCM6368 variants
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---
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arch/mips/bcm63xx/cpu.c | 4 ++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++
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2 files changed, 7 insertions(+)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -392,8 +392,12 @@ void __init bcm63xx_cpu_init(void)
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break;
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case BCM6368_CPU_ID:
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+ case BCM6369_CPU_ID:
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bcm63xx_regs_base = bcm6368_regs_base;
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bcm63xx_irqs = bcm6368_irqs;
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+
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+ /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
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+ bcm63xx_cpu_id = BCM6368_CPU_ID;
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break;
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default:
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panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -20,6 +20,7 @@
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#define BCM6361_CPU_ID 0x6361
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#define BCM6362_CPU_ID 0x6362
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#define BCM6368_CPU_ID 0x6368
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+#define BCM6369_CPU_ID 0x6369
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void __init bcm63xx_cpu_init(void);
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u32 bcm63xx_get_cpu_variant(void);
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@@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu
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(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
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#define BCMCPU_VARIANT_IS_6368() \
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(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
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+#define BCMCPU_VARIANT_IS_6369() \
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+ (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
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/*
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* While registers sets are (mostly) the same across 63xx CPU, base
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@ -11,7 +11,7 @@
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bcm_gpio_writel(val, GPIO_MODE_REG);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -621,6 +621,8 @@
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@@ -623,6 +623,8 @@
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#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
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#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
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#define GPIO_MODE_6358_UTOPIA (1 << 12)
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@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -931,6 +931,19 @@
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@@ -933,6 +933,19 @@
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#define ENETSW_PORTOV_FDX_MASK (1 << 1)
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#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
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@ -87,7 +87,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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return -ENODEV;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -672,6 +672,7 @@
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@@ -674,6 +674,7 @@
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#define GPIO_STRAPBUS_REG 0x40
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#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
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#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
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@ -95,7 +95,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
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#define STRAPBUS_6368_BOOT_SEL_NAND 0
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#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
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@@ -1513,6 +1514,7 @@
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@@ -1515,6 +1516,7 @@
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#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
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#define MISC_STRAPBUS_6328_REG 0x240
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