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package: uboot-sunxi: various changes - bump to 2016.03 - add bugfixes related to 2016.03 update - sync DTS files with mainline - add support for non-standard uEnv.txt - add initial support for Theobroma A31-yQ7 devboard

Browse source 
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

SVN-Revision: 49089
This commit is contained in:
Zoltan Herpai 2016-03-29 11:42:14 +00:00
parent d1aa4bfe1d
commit 2d4ebff3ad
25 changed files with 9835 additions and 210 deletions
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20
package/boot/uboot-sunxi/Makefile
View file

@ -9,13 +9,13 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=u-boot
PKG_VERSION:=2016.01
PKG_VERSION:=2016.03
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
http://mirror2.openwrt.org/sources \
ftp://ftp.denx.de/pub/u-boot
PKG_MD5SUM:=7d4f65fd43d4d706f5c5650e020d899d
PKG_MD5SUM:=973c1d896be751321cc3aafa564f64b2
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
@ -90,6 +90,10 @@ define uboot/Lamobo_R1
TITLE:=U-Boot for Lamobo R1
endef
define uboot/pangolin
TITLE:=U-Boot for Theobroma A31-yQ7 devboard
endef
define uboot/orangepi_plus
TITLE:=U-Boot for Orange Pi Plus (H3)
endef
@ -110,7 +114,8 @@ UBOOTS:= \
Linksprite_pcDuino \
Linksprite_pcDuino3 \
Lamobo_R1 \
orangepi_plus
orangepi_plus \
pangolin
define Package/uboot/template
define Package/uboot-sunxi-$(1)
@ -136,6 +141,13 @@ UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
endif
# check if any specialized uEnv bootconfig is required
ifeq ($(UBOOT_CONFIG),pangolin)
UENV:=pangolin
else
UENV:=default
endif
define Build/Configure
$(MAKE) -C $(PKG_BUILD_DIR) \
USE_PRIVATE_LIBGCC=yes $(UBOOT_CONFIG)_defconfig
@ -154,7 +166,7 @@ define Package/uboot/install/default
$(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-spl.bin
$(CP) $(PKG_BUILD_DIR)/u-boot-sunxi-with-spl.bin \
$(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-u-boot-with-spl.bin
$(CP) uEnv.txt \
$(CP) uEnv-$(UENV).txt \
$(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-uEnv.txt
mkimage -C none -A arm -T script -d $(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-uEnv.txt \
$(KERNEL_BUILD_DIR)/uboot-$(BOARD)-$(1)-boot.scr

394
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch Normal file
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@ -0,0 +1,394 @@
diff -ruN a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
--- a/arch/arm/dts/Makefile 2016-01-12 15:06:54.000000000 +0100
+++ b/arch/arm/dts/Makefile 2016-01-30 15:31:50.000000000 +0100
@@ -142,6 +142,7 @@
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31-pangolin.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-primo81.dtb \
sun6i-a31s-sinovoip-bpi-m2.dtb
diff -ruN a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi
--- a/arch/arm/dts/sun6i-a31.dtsi 2016-01-12 15:06:54.000000000 +0100
+++ b/arch/arm/dts/sun6i-a31.dtsi 2016-01-31 15:06:47.000000000 +0100
@@ -643,6 +643,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PB5", "PB6";
+ allwinner,function = "i2c3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
diff -ruN a/arch/arm/dts/sun6i-a31-pangolin.dts b/arch/arm/dts/sun6i-a31-pangolin.dts
--- a/arch/arm/dts/sun6i-a31-pangolin.dts 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/arm/dts/sun6i-a31-pangolin.dts 2016-02-09 01:21:44.965168099 +0100
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Theobroma Systems A31 Pangolin";
+ compatible = "tsd,a31-pangolin", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ snps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,m25p40";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ /* external pull-ups missing for some pins */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_pangolin: mmc0_cd_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ leds_pins_pangolin: led_pins@0 {
+ allwinner,pins = "PH7", "PC16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11",
+ "PC12","PC13","PC14","PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp221: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ dcdc1-supply = <&vcc_3v0>;
+ dcdc5-supply = <&vcc_dram>;
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ vcc_3v0: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ vdd_gpu: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ vdd_sys_dll: dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys-dll";
+ };
+
+ vcc_dram: dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+ };
+
+ vcc_wifi: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+
+ avcc: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PD23";
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+};
diff -ruN a/configs/pangolin_defconfig b/configs/pangolin_defconfig
--- a/configs/pangolin_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ b/configs/pangolin_defconfig 2016-01-30 14:43:59.000000000 +0100
@@ -0,0 +1,36 @@
+CONFIG_SUNXI_PANGOLIN=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-pangolin"
+CONFIG_VIDEO_VGA_VIA_LCD=y
+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CHANNELS=1
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=70
+CONFIG_AXP_DCDC1_VOLT=3300
+CONFIG_AXP_ALDO1_VOLT=0
+CONFIG_AXP_ALDO2_VOLT=1800
+CONFIG_AXP_ALDO3_VOLT=3000
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_AXP_ELDO1_VOLT=1200
+CONFIG_AXP_ELDO2_VOLT=2500
+CONFIG_AXP_ELDO3_VOLT=3300
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_CONS_INDEX=3
+# Vbus gpio for usb1
+CONFIG_USB1_VBUS_PIN=""
+# No Vbus gpio for usb2
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_IMLS=n
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SUNXI_SPI=y
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e155c4c..1b147b2 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -15,7 +15,6 @@ config SUNXI_GEN_SUN6I
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
-
choice
prompt "Sunxi SoC Variant"
optional
@@ -80,6 +79,14 @@ config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+choice
+ prompt "Sunxi Board Variant"
+ optional
+
+config SUNXI_PANGOLIN
+ bool "Theobroma A31 uQ7 Board"
+
+endchoice
config DRAM_CLK
int "sunxi dram clock speed"
--
cgit v0.10.2

1411
package/boot/uboot-sunxi/patches/010-dt-sync-files-with-kernel.patch Normal file
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60
package/boot/uboot-sunxi/patches/010-sunxi-support-smta.patch
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@ -1,60 +0,0 @@
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index dfb0a3e..7a6a3cc 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
obj-$(CONFIG_MACH_SUN6I) += tzpc.o
+obj-$(CONFIG_MACH_SUN8I) += tzpc.o
obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 5c9c69b..6c8a0fd 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -13,6 +13,15 @@ void tzpc_init(void)
{
struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
+#ifdef CONFIG_MACH_SUN6I
/* Enable non-secure access to the RTC */
- writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+ writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_H3
+ /* Enable non-secure access to all peripherals */
+ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
+ writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
+ writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
+#endif
}
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
index ba4d43b..95c55cd 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -13,10 +13,21 @@ struct sunxi_tzpc {
u32 decport0_status; /* 0x04 Status of decode protection port 0 */
u32 decport0_set; /* 0x08 Set decode protection port 0 */
u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
+ /* For A80 and later SoCs */
+ u32 decport1_status; /* 0x10 Status of decode protection port 1 */
+ u32 decport1_set; /* 0x14 Set decode protection port 1 */
+ u32 decport1_clear; /* 0x18 Clear decode protection port 1 */
+ u32 decport2_status; /* 0x1c Status of decode protection port 2 */
+ u32 decport2_set; /* 0x20 Set decode protection port 2 */
+ u32 decport2_clear; /* 0x24 Clear decode protection port 2 */
};
#endif
-#define SUNXI_TZPC_DECPORT0_RTC (1 << 1)
+#define SUN6I_TZPC_DECPORT0_RTC (1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f
void tzpc_init(void);

7354
package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch Normal file
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83
package/boot/uboot-sunxi/patches/011-sunxi-support-h3-ccu.patch
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@ -1,83 +0,0 @@
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 47fb70f..5cc5d25 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -14,12 +14,17 @@
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
+__weak void clock_init_sec(void)
+{
+}
+
int clock_init(void)
{
#ifdef CONFIG_SPL_BUILD
clock_init_safe();
#endif
clock_init_uart();
+ clock_init_sec();
return 0;
}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 4501884..d0085e8 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,6 +45,19 @@ void clock_init_safe(void)
}
#endif
+void clock_init_sec(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#ifdef CONFIG_MACH_SUN8I_H3
+ setbits_le32(&ccm->ccu_sec_switch,
+ CCM_SEC_SWITCH_MBUS_NONSEC |
+ CCM_SEC_SWITCH_BUS_NONSEC |
+ CCM_SEC_SWITCH_PLL_NONSEC);
+#endif
+}
+
void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca58ae..6c0573f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -30,6 +30,7 @@ int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
+void clock_init_sec(void);
void clock_init_uart(void);
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 5c76275..554d858 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
u32 reserved24;
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
+ u32 reserved25[5];
+ u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
};
/* apb2 bit field */
@@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
+
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);

40
package/boot/uboot-sunxi/patches/012-sun6i-fix-clock_twi_onoff.patch Normal file
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@ -0,0 +1,40 @@
From 730d2f3a41c5ccae71b5008fffdf697d143be68c Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Mar 2016 20:44:51 +0100
Subject: [PATCH] sunxi: Fix clock_twi_onoff for sun6i
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 700b605..4e1e1a4 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -100,13 +100,18 @@ int clock_twi_onoff(int port, int state)
return 0;
}
- /* set the apb clock gate for twi */
- if (state)
+ /* set the apb clock gate and reset for twi */
+ if (state) {
setbits_le32(&ccm->apb2_gate,
CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
- else
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
clrbits_le32(&ccm->apb2_gate,
CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+ }
return 0;
}

22
package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch
View file

@ -1,22 +0,0 @@
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 4ff46e4..90b5bfd 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -106,7 +106,7 @@ psci_fiq_enter:
str r10, [r8, #0x100]
timer_wait r10, ONE_MS
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Activate power clamp
lsl r12, r9, #2 @ x4
add r12, r12, r8
@@ -170,7 +170,7 @@ psci_cpu_on:
movw r0, #(SUNXI_PRCM_BASE & 0xffff)
movt r0, #(SUNXI_PRCM_BASE >> 16)
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
@ Release power clamp
lsl r5, r1, #2 @ 1 register per CPU
add r5, r5, r0 @ PRCM

26
package/boot/uboot-sunxi/patches/013-enable-realtek-phy.patch Normal file
View file

@ -0,0 +1,26 @@
From 1eae8f66ff749409eb96e2f3f3387c56232d0b8a Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Mar 2016 13:46:22 +0100
Subject: [PATCH] sunxi: Enable realtek phy support
Enable building of drivers/net/phy/realtek.c so that realtek phys
get properly initialized.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b26363d..ea15e37 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -310,6 +310,7 @@ extern int soft_i2c_gpio_scl;
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
+#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_USB_EHCI_HCD

16
package/boot/uboot-sunxi/patches/013-sunxi-enable-booting-nonsec_HYP-on-h3.patch
View file

@ -1,16 +0,0 @@
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9d67847..28e6bb4 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -71,8 +71,11 @@ config MACH_SUN8I_A33
config MACH_SUN8I_H3
bool "sun8i (Allwinner H3)"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"

135
package/boot/uboot-sunxi/patches/014-fix-gmac-init.patch Normal file
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@ -0,0 +1,135 @@
From fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 17 Mar 2016 13:53:03 +0100
Subject: [PATCH] sunxi: Fix gmac not working due to cpu_eth_init no longer
being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
---
arch/arm/cpu/armv7/sunxi/board.c | 28 +---------------------------
arch/arm/include/asm/arch-sunxi/sys_proto.h | 6 +++++-
board/sunxi/board.c | 5 +++++
board/sunxi/gmac.c | 14 +-------------
4 files changed, 12 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index e80785b..7653148 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -152,6 +152,7 @@ void s_init(void)
timer_init();
gpio_init();
i2c_init_board();
+ eth_init_board();
}
#ifdef CONFIG_SPL_BUILD
@@ -259,30 +260,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_request(CONFIG_MACPWR, "macpwr");
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index 9df3744..a373319 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -24,6 +24,10 @@ void sdelay(unsigned long);
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
-int sunxi_gmac_initialize(bd_t *bis);
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
+void eth_init_board(void);
+#else
+static inline void eth_init_board(void) {}
+#endif
#endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 80eae9c..e16718f 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -90,6 +90,11 @@ int board_init(void)
if (ret)
return ret;
+#ifdef CONFIG_MACPWR
+ gpio_request(CONFIG_MACPWR, "macpwr");
+ gpio_direction_output(CONFIG_MACPWR, 1);
+#endif
+
/* Uses dm gpio code so do this here and not in i2c_init_board() */
return soft_i2c_board_init();
}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 4e222d8..69eb8ff 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -6,7 +6,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-int sunxi_gmac_initialize(bd_t *bis)
+void eth_init_board(void)
{
int pin;
struct sunxi_ccm_reg *const ccm =
@@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis)
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
-
-#ifdef CONFIG_DM_ETH
- return 0;
-#else
-# ifdef CONFIG_RGMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-# elif defined CONFIG_GMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-# else
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
-# endif
-#endif
}

82
package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch Normal file
View file

@ -0,0 +1,82 @@
From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 21 Mar 2016 14:44:35 +0100
Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
working
The 2nd usb controller on sun4i/sun7i has its base address 0x8000
bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
are interleaved with the ohci clk-gates introducing a hole between
the clks for usb1 and usb2.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index cf3dcc4..677a5d3 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -17,6 +17,14 @@
#include <dm.h>
#include "ehci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ehci_sunxi_priv {
struct ehci_ctrl ehci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev)
#ifdef CONFIG_MACH_SUN8I_H3
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 1b1f651..d4fb95a 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -17,6 +17,14 @@
#include <usb.h>
#include "ohci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ohci_sunxi_priv {
ohci_t ohci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev)
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
- priv->usb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->usb_gate_mask <<= priv->phy_index;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);

33
package/boot/uboot-sunxi/patches/016-spl-print-mmc-slot.patch Normal file
View file

@ -0,0 +1,33 @@
From 8f10b5c65611e6c15a113bf63289b6696452f90d Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 20 Mar 2016 14:17:10 +0100
Subject: [PATCH] spl: Print from which mmc slot spl is trying to boot
On some sunxi boards (and presumably also non sunxi boards) u-boot can
be either loaded from a sdcard in a micro-sd slot, or from eMMC.
Print which MMC spl tries to boot from, to help debugging.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
common/spl/spl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index e5167bf..82e7f58 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -210,9 +210,9 @@ struct boot_device_name boot_name_table[] = {
{ BOOT_DEVICE_RAM, "RAM" },
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
- { BOOT_DEVICE_MMC1, "MMC" },
- { BOOT_DEVICE_MMC2, "MMC" },
- { BOOT_DEVICE_MMC2_2, "MMC" },
+ { BOOT_DEVICE_MMC1, "MMC1" },
+ { BOOT_DEVICE_MMC2, "MMC2" },
+ { BOOT_DEVICE_MMC2_2, "MMC2_2" },
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
{ BOOT_DEVICE_NAND, "NAND" },

43
package/boot/uboot-sunxi/patches/017-usb-add-support-for-usb3-vbus-pin.patch Normal file
View file

@ -0,0 +1,43 @@
From 60fa63012fcdc3c4ec1497bf5e358f0a90b40949 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 18 Mar 2016 08:42:01 +0100
Subject: [PATCH] sunxi: Add support for USB vbus pin for USB3
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/usb_phy.c | 1 +
board/sunxi/Kconfig | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 6ac96cc..0749fbd 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
}
return -EINVAL;
}
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5e9d3af..5e72fac 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -342,6 +342,12 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
+config USB3_VBUS_PIN
+ string "Vbus enable pin for usb3 (ehci2)"
+ default ""
+ ---help---
+ See USB1_VBUS_PIN help text.
+
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I

35
package/boot/uboot-sunxi/patches/018-usb-specify-vbus-pins-on-orangepis.patch Normal file
View file

@ -0,0 +1,35 @@
From ce0d0926758f631fdd655d438acd32d5935d43a4 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 18 Mar 2016 08:45:21 +0100
Subject: [PATCH] sunxi: Specify USB vbus pins for orangepi boards
This fixes the USB ports not working on the orangepi_plus and stops us
from messing with gpio-s which we should not touch on the orangepi_pc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
configs/orangepi_pc_defconfig | 3 +++
configs/orangepi_plus_defconfig | 1 +
2 files changed, 4 insertions(+)
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index aaf0f68..4e9051d 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -14,3 +14,6 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index e52dcfc..6ecb30e 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PG13"

35
package/boot/uboot-sunxi/patches/019-sid-add-efuse-support-for-h3-a83t.patch Normal file
View file

@ -0,0 +1,35 @@
From 70fe24ed93fa90eb407d18a5fc9d9ad85ac9184c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 27 Jan 2016 16:34:43 +0800
Subject: [PATCH] sunxi: Support SID e-fuses on A83T and H3
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index b6e11eb..65c0441 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -82,7 +82,14 @@
#define SUNXI_AD_DA_BASE 0x01c22c00
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
+
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE 0x01c14200
+#else
#define SUNXI_SID_BASE 0x01c23800
+#endif
+
#define SUNXI_SJTAG_BASE 0x01c23c00
#define SUNXI_TP_BASE 0x01c25000

25
package/boot/uboot-sunxi/patches/020-boot-display-board-model-on-startup.patch Normal file
View file

@ -0,0 +1,25 @@
From 2af25b747340c6c8f6a6b9e27632db577bf4da52 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 22 Feb 2016 22:55:46 -0700
Subject: [PATCH] sunxi: Display the board model on start-up
It is useful to know which sunxi board you are booting. Display this on
start-up to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ff356e3..b26363d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -174,6 +174,7 @@
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
#define CONFIG_IDENT_STRING " Allwinner Technology"
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */

25
package/boot/uboot-sunxi/patches/020-fix-bananapro-sata-LDO4.patch
View file

@ -1,25 +0,0 @@
From 54be0f057825b886af008d8d43a97802e5537ab6 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 22 Jan 2016 14:55:47 +0100
Subject: [PATCH] sunxi: Bananapro: Set LDO4 to 2.5V
According to the Bananapro schematic VDD25-SATA either comes from a
dedicated WL2003E25-5 LTO, or it is connected to LDO4 via a
0 Ohm resistor.
In practice it seems that LDO4 is used, so enable it and set it to 2.5V.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
configs/Bananapro_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 40588b9..4f4a07b 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -17,3 +17,4 @@ CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO4_VOLT=2500

37
package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch Normal file
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@ -0,0 +1,37 @@
From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 6 Jan 2015 15:47:18 +0100
Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
This change syncs up the multipliers and dividers used to initialize
PLL1 (i.e. the fast clock driving the ARM cores) with the values used
in Allwinner's Boot1 on sun6i.
More specifically, the following settings are now used:
* up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
* up to 1152MHz: mul=3, div=2 (unchanged)
* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index cfb32b4..2986539 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -102,11 +102,12 @@ void clock_set_pll1(unsigned int clk)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;
- int k = 1;
- int m = 1;
+ int k = 2;
+ int m = 2;
if (clk > 1152000000) {
- k = 2;
+ k = 4;
+ m = 2;
} else if (clk > 768000000) {
k = 3;
m = 2;
--
cgit v0.10.2

77
package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch Normal file
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@ -0,0 +1,77 @@
From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 6 Jan 2015 21:26:44 +0100
Subject: sun6i: Fix and document PLL LDO voltage selection
The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
their meaning reversed. This is fixed by this change-set. With this
changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
as setting the voltage to 1.37v (which it had done all along, even
though stating a different target voltage).
After changing the PLL LDO setting, it will take a little while for
the voltage output to settle. A sdelay()-based loop waits the same
order of magnitude as Boot1.
Furthermore, a bit of documentation is added to clarify that the
required setting for the PLL LDO is 1.37v as per the A31 manual.
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index fa7ebd8..3a6e56e 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -24,14 +24,27 @@ void clock_init_safe(void)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- /* Set PLL ldo voltage without this PLL6 does not work properly */
+ /* Set PLL ldo voltage without this PLL6 does not work properly.
+ *
+ * As the A31 manual states, that "before enable PLL, PLLVDD
+ * LDO should be set to 1.37v", we need to configure this to 2.5v
+ * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
+ */
clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
PRCM_PLL_CTRL_LDO_KEY);
clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+ /* Give the PLL LDO voltage setting some time to take hold.
+ * Notes:
+ * 1) We need to use sdelay() as the timers aren't set up yet.
+ * 2) The 100k iterations come from Boot1, which spin's for 100k
+ * iterations through a loop.
+ */
+ sdelay(100000);
+
clock_set_pll1(408000000);
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 82ed541..41a62a4 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -111,13 +111,13 @@
#define PRCM_PLL_CTRL_LDO_OUT_MASK \
__PRCM_PLL_CTRL_LDO_OUT(0x7)
/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
--
cgit v0.10.2

21
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch Normal file
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@ -0,0 +1,21 @@
From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:52:01 +0200
Subject: sun6i: define alternate-function for UART2 on GPG
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 8e67b3b..1fbf494 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -177,6 +177,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
+#define SUN6I_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN4I_GPH_SDC1 5
--
cgit v0.10.2

37
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch Normal file
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@ -0,0 +1,37 @@
From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:53:11 +0200
Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 5f39aa0..99675c3 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -76,6 +76,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 9576bc1..bda4059 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -260,6 +260,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
--
cgit v0.10.2

28
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch Normal file
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@ -0,0 +1,28 @@
From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:59:38 +0200
Subject: ARM: sunxi: Make CONS_INDEX configurable
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 2a1cd3c..e155c4c 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -209,6 +209,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 5
+ default 1
+ ---help---
+ Defines the UART port used for serial output. It starts at 1 so UART0 is 1,
+ UART1 is 2 and so on.
+
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
default n
--
cgit v0.10.2

0
package/boot/uboot-sunxi/uEnv.txt → package/boot/uboot-sunxi/uEnv-default.txt
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6
package/boot/uboot-sunxi/uEnv-pangolin.txt Normal file
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@ -0,0 +1,6 @@
setenv fdt_high ffffffff
setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage
setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb
setenv bootargs console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootwait
setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
run uenvcmd