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convert aruba to the new structure

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SVN-Revision: 7284
This commit is contained in:
Imre Kaloz 2007-05-20 19:32:31 +00:00
parent 07009a08e0
commit 06fb3b2848
42 changed files with 8218 additions and 13433 deletions
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49
target/linux/aruba-2.6/files/arch/mips/aruba/Makefile Normal file
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###############################################################################
#
# BRIEF MODULE DESCRIPTION
# Makefile for IDT EB434 BSP
#
# Copyright 2004 IDT Inc. (rischelp@idt.com)
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 2 of the License, or (at your
# option) any later version.
#
# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 675 Mass Ave, Cambridge, MA 02139, USA.
#
#
###############################################################################
# May 2004 rkt, neb
#
# Initial Release
#
#
#
###############################################################################
# .S.s:
# $(CPP) $(CFLAGS) $< -o $*.s
# .S.o:
# $(CC) $(CFLAGS) -c $< -o $*.o
obj-y := prom.o setup.o irq.o time.o flash_lock.o
obj-$(CONFIG_SERIAL_8250) += serial.o
subdir-y += nvram
obj-y += nvram/built-in.o

27
target/linux/aruba-2.6/files/arch/mips/aruba/flash_lock.c Normal file
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#include <linux/module.h>
#include <linux/types.h>
#include <asm/bootinfo.h>
#define AP70_PROT_ADDR 0xb8010008
#define AP70_PROT_DATA 0x8
#define AP60_PROT_ADDR 0xB8400000
#define AP60_PROT_DATA 0x04000000
void unlock_ap60_70_flash(void)
{
volatile __u32 val;
switch (mips_machtype) {
case MACH_ARUBA_AP70:
val = *(volatile __u32 *)AP70_PROT_ADDR;
val &= ~(AP70_PROT_DATA);
*(volatile __u32 *)AP70_PROT_ADDR = val;
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
default:
val = *(volatile __u32 *)AP60_PROT_ADDR;
val &= ~(AP60_PROT_DATA);
*(volatile __u32 *)AP60_PROT_ADDR = val;
break;
}
}

285
target/linux/aruba-2.6/files/arch/mips/aruba/irq.c Normal file
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#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/delay.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/idt-boards/rc32434/rc32434.h>
#include <asm/idt-boards/rc32434/rc32434_gpio.h>
#include <asm/irq.h>
extern void aruba_timer_interrupt(struct pt_regs *regs);
typedef struct {
u32 mask;
volatile u32 *base_addr;
} intr_group_t;
static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
{0x00000000, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
};
#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003014)))
#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)(0xbc003014))) = (val), READ_MASK_MERLOT())
static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
{0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
{0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
{0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
{0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
{0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
};
#define READ_PEND_MUSCAT(base) (*(base))
#define READ_MASK_MUSCAT(base) (*(base + 2))
#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
static inline int group_to_ip(unsigned int group)
{
switch (mips_machtype) {
case MACH_ARUBA_AP70:
return group + 2;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
default:
return 6;
}
}
static inline void enable_local_irq(unsigned int irq)
{
clear_c0_cause(0x100 << irq);
set_c0_status(0x100 << irq);
irq_enable_hazard();
}
static inline void disable_local_irq(unsigned int irq)
{
clear_c0_status(0x100 << irq);
clear_c0_cause(0x100 << irq);
irq_disable_hazard();
}
static inline void aruba_irq_enable(unsigned int irq)
{
unsigned long flags;
unsigned int group, intr_bit;
volatile unsigned int *addr;
local_irq_save(flags);
if (irq < GROUP0_IRQ_BASE) {
enable_local_irq(irq);
} else {
int ip = irq - GROUP0_IRQ_BASE;
switch (mips_machtype) {
case MACH_ARUBA_AP70:
if (irq >= GROUP4_IRQ_BASE)
idt_gpio->gpioistat &= ~(1 << (irq - GROUP4_IRQ_BASE));
// irqs are in groups of 32
// ip is set to the remainder
group = ip >> 5;
ip &= 0x1f;
// bit -> 0 = unmask
intr_bit = 1 << ip;
addr = intr_group_muscat[group].base_addr;
WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
group = 0;
// bit -> 1 = unmasked
intr_bit = 1 << ip;
addr = intr_group_merlot[group].base_addr;
WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
break;
}
enable_local_irq(group_to_ip(group));
}
back_to_back_c0_hazard();
local_irq_restore(flags);
}
static void aruba_irq_disable(unsigned int irq)
{
unsigned long flags;
unsigned int group, intr_bit, mask;
volatile unsigned int *addr;
local_irq_save(flags);
if (irq < GROUP0_IRQ_BASE) {
disable_local_irq(irq);
} else {
int ip = irq - GROUP0_IRQ_BASE;
switch (mips_machtype) {
case MACH_ARUBA_AP70:
idt_gpio->gpioistat &= ~(1 << ip);
// irqs are in groups of 32
// ip is set to the remainder
group = ip >> 5;
ip &= 0x1f;
// bit -> 1 = mask
intr_bit = 1 << ip;
addr = intr_group_muscat[group].base_addr;
mask = READ_MASK_MUSCAT(addr);
mask |= intr_bit;
WRITE_MASK_MUSCAT(addr, mask);
if (mask == intr_group_muscat[group].mask) {
disable_local_irq(group_to_ip(group));
}
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
group = 0;
// bit -> 0 = masked
intr_bit = 1 << ip;
addr = intr_group_merlot[group].base_addr;
mask = READ_MASK_MERLOT(addr);
mask &= ~intr_bit;
WRITE_MASK_MERLOT(addr, mask);
if (mask == intr_group_merlot[group].mask) {
disable_local_irq(group_to_ip(group));
}
break;
}
}
back_to_back_c0_hazard();
local_irq_restore(flags);
}
static unsigned int aruba_irq_startup(unsigned int irq)
{
aruba_irq_enable(irq);
return 0;
}
#define aruba_irq_shutdown aruba_irq_disable
static void aruba_irq_ack(unsigned int irq)
{
aruba_irq_disable(irq);
}
static void aruba_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
aruba_irq_enable(irq);
}
static struct hw_interrupt_type aruba_irq_type = {
.typename = "ARUBA",
.startup = aruba_irq_startup,
.shutdown = aruba_irq_shutdown,
.enable = aruba_irq_enable,
.disable = aruba_irq_disable,
.ack = aruba_irq_ack,
.end = aruba_irq_end,
};
void __init arch_init_irq(void)
{
int i;
printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
memset(irq_desc, 0, sizeof(irq_desc));
for (i = 0; i < RC32434_NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].chip = &aruba_irq_type;
spin_lock_init(&irq_desc[i].lock);
}
}
/* Main Interrupt dispatcher */
void plat_irq_dispatch(struct pt_regs *regs)
{
unsigned int pend, group, ip;
volatile unsigned int *addr;
unsigned long cp0_cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
if (cp0_cause & CAUSEF_IP7)
return aruba_timer_interrupt(regs);
if(cp0_cause == 0) {
printk("INTERRUPT(S) FIRED WHILE MASKED\n");
#ifdef ARUBA_DEBUG
// debuging use -- figure out which interrupt(s) fired
cp0_cause = read_c0_cause() & CAUSEF_IP;
while (cp0_cause) {
unsigned long intr_bit;
unsigned int irq_nr;
intr_bit = (31 - rc32434_clz(cp0_cause));
irq_nr = intr_bit - GROUP0_IRQ_BASE;
printk(" ---> MASKED IRQ %d\n",irq_nr);
cp0_cause &= ~(1 << intr_bit);
}
#endif
return;
}
switch (mips_machtype) {
case MACH_ARUBA_AP70:
if ((ip = (cp0_cause & 0x7c00))) {
group = 21 - rc32434_clz(ip);
addr = intr_group_muscat[group].base_addr;
pend = READ_PEND_MUSCAT(addr);
pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
pend = 39 - rc32434_clz(pend);
do_IRQ(pend + (group << 5));
}
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
default:
if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
// Misc Interrupt
group = 0;
addr = intr_group_merlot[group].base_addr;
pend = READ_PEND_MERLOT(addr);
pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
pend = 31 - rc32434_clz(pend);
do_IRQ(pend + GROUP0_IRQ_BASE);
}
if ((ip = (cp0_cause & 0x3c00))) { // irq 2-5
pend = 31 - rc32434_clz(ip);
do_IRQ(pend - GROUP0_IRQ_BASE);
}
break;
}
}

46
target/linux/aruba-2.6/files/arch/mips/aruba/nvram/Makefile Normal file
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###############################################################################
#
# BRIEF MODULE DESCRIPTION
# Makefile for IDT EB434 nvram access routines
#
# Copyright 2004 IDT Inc. (rischelp@idt.com)
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 2 of the License, or (at your
# option) any later version.
#
# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 675 Mass Ave, Cambridge, MA 02139, USA.
#
#
###############################################################################
# May 2004 rkt, neb
#
# Initial Release
#
#
#
###############################################################################
obj-y := nvram434.o
obj-m := $(O_TARGET)

392
target/linux/aruba-2.6/files/arch/mips/aruba/nvram/nvram434.c Normal file
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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* nvram interface routines.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/ctype.h>
#include <linux/string.h>
//#include <asm/ds1553rtc.h>
#include "nvram434.h"
#define NVRAM_BASE 0xbfff8000
extern void setenv (char *e, char *v, int rewrite);
extern void unsetenv (char *e);
extern void mapenv (int (*func)(char *, char *));
extern char *getenv (char *s);
extern void purgeenv(void);
static void nvram_initenv(void);
static unsigned char
nvram_getbyte(int offs)
{
return(*((unsigned char*)(NVRAM_BASE + offs)));
}
static void
nvram_setbyte(int offs, unsigned char val)
{
unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
*nvramDataPointer = val;
}
/*
* BigEndian!
*/
static unsigned short
nvram_getshort(int offs)
{
return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
}
static void
nvram_setshort(int offs, unsigned short val)
{
nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
}
#if 0
static unsigned int
nvram_getint(int offs)
{
unsigned int val;
val = nvram_getbyte(offs) << 24;
val |= nvram_getbyte(offs + 1) << 16;
val |= nvram_getbyte(offs + 2) << 8;
val |= nvram_getbyte(offs + 3);
return(val);
}
static void
nvram_setint(int offs, unsigned int val)
{
nvram_setbyte(offs, val >> 24);
nvram_setbyte(offs + 1, val >> 16);
nvram_setbyte(offs + 2, val >> 8);
nvram_setbyte(offs + 3, val);
}
#endif
/*
* calculate NVRAM checksum
*/
static unsigned short
nvram_calcsum(void)
{
unsigned short sum = NV_MAGIC;
int i;
for (i = ENV_BASE; i < ENV_TOP; i += 2)
sum += nvram_getshort(i);
return(sum);
}
/*
* update the nvram checksum
*/
static void
nvram_updatesum (void)
{
nvram_setshort(NVOFF_CSUM, nvram_calcsum());
}
/*
* test validity of nvram by checksumming it
*/
static int
nvram_isvalid(void)
{
static int is_valid;
if (is_valid)
return(1);
if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
printk("nvram_isvalid FAILED\n");
//nvram_initenv();
}
is_valid = 1;
return(1);
}
/* return nvram address of environment string */
static int
nvram_matchenv(char *s)
{
int envsize, envp, n, i, varsize;
char *var;
envsize = nvram_getshort(NVOFF_ENVSIZE);
if (envsize > ENV_AVAIL)
return(0); /* sanity */
envp = ENV_BASE;
if ((n = strlen (s)) > 255)
return(0);
while (envsize > 0) {
varsize = nvram_getbyte(envp);
if (varsize == 0 || (envp + varsize) > ENV_TOP)
return(0); /* sanity */
for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
char c1 = nvram_getbyte(i);
char c2 = *var;
if (islower(c1))
c1 = toupper(c1);
if (islower(c2))
c2 = toupper(c2);
if (c1 != c2)
break;
}
if (i > envp + n) { /* match so far */
if (n == varsize - 1) /* match on boolean */
return(envp);
if (nvram_getbyte(i) == '=') /* exact match on variable */
return(envp);
}
envsize -= varsize;
envp += varsize;
}
return(0);
}
static void nvram_initenv(void)
{
nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
nvram_setshort(NVOFF_ENVSIZE, 0);
nvram_updatesum();
}
static void
nvram_delenv(char *s)
{
int nenvp, envp, envsize, nbytes;
envp = nvram_matchenv(s);
if (envp == 0)
return;
nenvp = envp + nvram_getbyte(envp);
envsize = nvram_getshort(NVOFF_ENVSIZE);
nbytes = envsize - (nenvp - ENV_BASE);
nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
while (nbytes--) {
nvram_setbyte(envp, nvram_getbyte(nenvp));
envp++;
nenvp++;
}
nvram_updatesum();
}
static int
nvram_setenv(char *s, char *v)
{
int ns, nv, total;
int envp;
if (!nvram_isvalid())
return(-1);
nvram_delenv(s);
ns = strlen(s);
if (ns == 0)
return (-1);
if (v && *v) {
nv = strlen(v);
total = ns + nv + 2;
}
else {
nv = 0;
total = ns + 1;
}
if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
return(-1);
envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
nvram_setbyte(envp, (unsigned char) total);
envp++;
while (ns--) {
nvram_setbyte(envp, *s);
envp++;
s++;
}
if (nv) {
nvram_setbyte(envp, '=');
envp++;
while (nv--) {
nvram_setbyte(envp, *v);
envp++;
v++;
}
}
nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
nvram_updatesum();
return 0;
}
static char *
nvram_getenv(char *s)
{
static char buf[256]; /* FIXME: this cannot be static */
int envp, ns, nbytes, i;
if (!nvram_isvalid())
return "INVALID NVRAM"; //((char *)0);
envp = nvram_matchenv(s);
if (envp == 0)
return "NOT FOUND"; //((char *)0);
ns = strlen(s);
if (nvram_getbyte(envp) == ns + 1) /* boolean */
buf[0] = '\0';
else {
nbytes = nvram_getbyte(envp) - (ns + 2);
envp += ns + 2;
for (i = 0; i < nbytes; i++)
buf[i] = nvram_getbyte(envp++);
buf[i] = '\0';
}
return(buf);
}
static void
nvram_unsetenv(char *s)
{
if (!nvram_isvalid())
return;
nvram_delenv(s);
}
/*
* apply func to each string in environment
*/
static void
nvram_mapenv(int (*func)(char *, char *))
{
int envsize, envp, n, i, seeneql;
char name[256], value[256];
char c, *s;
if (!nvram_isvalid())
return;
envsize = nvram_getshort(NVOFF_ENVSIZE);
envp = ENV_BASE;
while (envsize > 0) {
value[0] = '\0';
seeneql = 0;
s = name;
n = nvram_getbyte(envp);
for (i = envp + 1; i < envp + n; i++) {
c = nvram_getbyte(i);
if ((c == '=') && !seeneql) {
*s = '\0';
s = value;
seeneql = 1;
continue;
}
*s++ = c;
}
*s = '\0';
(*func)(name, value);
envsize -= n;
envp += n;
}
}
#if 0
static unsigned int
digit(char c)
{
if ('0' <= c && c <= '9')
return (c - '0');
if ('A' <= c && c <= 'Z')
return (10 + c - 'A');
if ('a' <= c && c <= 'z')
return (10 + c - 'a');
return (~0);
}
#endif
/*
* Wrappers to allow 'special' environment variables to get processed
*/
void
setenv(char *e, char *v, int rewrite)
{
if (nvram_getenv(e) && !rewrite)
return;
nvram_setenv(e, v);
}
char *
getenv(char *e)
{
return(nvram_getenv(e));
}
void
unsetenv(char *e)
{
nvram_unsetenv(e);
}
void
purgeenv()
{
int i;
unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
for (i = ENV_BASE; i < ENV_TOP; i++)
*nvramDataPointer++ = 0;
nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
nvram_setshort(NVOFF_ENVSIZE, 0);
nvram_setshort(NVOFF_CSUM, NV_MAGIC);
}
void
mapenv(int (*func)(char *, char *))
{
nvram_mapenv(func);
}

66
target/linux/aruba-2.6/files/arch/mips/aruba/nvram/nvram434.h Normal file
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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* nvram definitions.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef _NVRAM_
#define _NVRAM_
#define NVOFFSET 0 /* use all of NVRAM */
/* Offsets to reserved locations */
/* size description */
#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
#define NV_MAGIC 0xdeaf /* nvram magic number */
#define NV_RESERVED 6 /* number of reserved bytes */
#undef NVOFF_ETHADDR
#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
/* number of bytes available for environment */
#define ENV_BASE (NVOFFSET + NV_RESERVED)
#define ENV_TOP 0x2000
#define ENV_AVAIL (ENV_TOP - ENV_BASE)
#endif /* _NVRAM_ */

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* prom interface routines
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/console.h>
#include <asm/bootinfo.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <linux/serial.h>
#include <linux/serialP.h>
#include <asm/serial.h>
#include <linux/ioport.h>
unsigned int idt_cpu_freq;
EXPORT_SYMBOL(idt_cpu_freq);
unsigned int arch_has_pci=0;
/* Kernel Boot parameters */
static unsigned char bootparm[] =
"init=/etc/preinit noinitrd "
"mtdparts=physmap-flash.0:3520k@0x080000(kernel),2752k@0x140000(rootfs),8k@0x3f8000(NVRAM) "
"console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=squashfs,jffs2 ";
extern unsigned long mips_machgroup;
extern unsigned long mips_machtype;
extern void setup_serial_port(void);
extern char * getenv(char *e);
/* IDT 79EB434 memory map -- we really should be auto sizing it */
#define RAM_SIZE 32*1024*1024
char *__init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
void __init prom_init(void)
{
char *boardname;
sprintf(arcs_cmdline, "%s", bootparm);
/* set our arch type */
mips_machgroup = MACH_GROUP_ARUBA;
mips_machtype = MACH_ARUBA_UNKNOWN;
boardname=getenv("boardname");
if (!strcmp(boardname,"Muscat")) {
mips_machtype = MACH_ARUBA_AP70;
idt_cpu_freq = 133000000;
arch_has_pci=1;
} else if (!strcmp(boardname,"Mataro")) {
mips_machtype = MACH_ARUBA_AP65;
idt_cpu_freq = 110000000;
} else if (!strcmp(boardname,"Merlot")) {
mips_machtype = MACH_ARUBA_AP60;
idt_cpu_freq = 90000000;
}
/* turn on the console */
setup_serial_port();
/*
* give all RAM to boot allocator,
* except where the kernel was loaded
*/
add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
}
void prom_free_prom_memory(void)
{
printk("stubbed prom_free_prom_memory()\n");
}

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Serial port initialisation.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <asm/time.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/serial.h>
#include <asm/idt-boards/rc32434/rc32434.h>
extern int __init early_serial_setup(struct uart_port *port);
#define BASE_BAUD (1843200 / 16)
extern unsigned int idt_cpu_freq;
extern int __init setup_serial_port(void)
{
static struct uart_port serial_req[2];
memset(serial_req, 0, sizeof(serial_req));
serial_req[0].type = PORT_16550A;
serial_req[0].line = 0;
serial_req[0].flags = STD_COM_FLAGS;
serial_req[0].iotype = SERIAL_IO_MEM;
serial_req[0].regshift = 2;
switch (mips_machtype) {
case MACH_ARUBA_AP70:
serial_req[0].irq = 104;
serial_req[0].mapbase = KSEG1ADDR(0x18058003);
serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
serial_req[0].uartclk = idt_cpu_freq;
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
default:
serial_req[0].irq = 12;
serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
serial_req[0].uartclk = idt_cpu_freq / 2;
break;
}
early_serial_setup(&serial_req[0]);
return(0);
}

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* setup routines for IDT EB434 boards
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <linux/ioport.h>
#include <asm/mipsregs.h>
#include <asm/pgtable.h>
#include <asm/reboot.h>
#include <asm/addrspace.h> /* for KSEG1ADDR() */
#include <asm/idt-boards/rc32434/rc32434.h>
#include <linux/pm.h>
extern char *__init prom_getcmdline(void);
extern void (*board_time_init) (void);
extern void aruba_time_init(void);
extern void aruba_reset(void);
#define epldMask ((volatile unsigned char *)0xB900000d)
static void aruba_machine_restart(char *command)
{
switch (mips_machtype) {
case MACH_ARUBA_AP70:
*(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
break;
case MACH_ARUBA_AP65:
case MACH_ARUBA_AP60:
default:
/* Reset*/
*((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
udelay(100);
*((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
udelay(100);
*((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
break;
}
}
static void aruba_machine_halt(void)
{
for (;;) continue;
}
extern char * getenv(char *e);
extern void unlock_ap60_70_flash(void);
void __init plat_mem_setup(void)
{
board_time_init = aruba_time_init;
_machine_restart = aruba_machine_restart;
_machine_halt = aruba_machine_halt;
pm_power_off = aruba_machine_halt;
set_io_port_base(KSEG1);
/* Enable PCI interrupts in EPLD Mask register */
*epldMask = 0x0;
*(epldMask + 1) = 0x0;
write_c0_wired(0);
unlock_ap60_70_flash();
printk("BOARD - %s\n",getenv("boardname"));
}
int page_is_ram(unsigned long pagenr)
{
return 1;
}
const char *get_system_type(void)
{
switch (mips_machtype) {
case MACH_ARUBA_AP70:
return "Aruba AP70";
case MACH_ARUBA_AP65:
return "Aruba AP65";
case MACH_ARUBA_AP60:
return "Aruba AP60/AP61";
default:
return "Aruba UNKNOWN";
}
}
EXPORT_SYMBOL(get_system_type);

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* timer routines for IDT EB434 boards
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <linux/timex.h>
#include <linux/param.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/time.h>
#include <asm/hardirq.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/debug.h>
#include <asm/time.h>
#include <asm/idt-boards/rc32434/rc32434.h>
static unsigned long r4k_offset; /* Amount to incr compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
extern unsigned int idt_cpu_freq;
static unsigned long __init cal_r4koff(void)
{
mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
return (mips_hpt_frequency / HZ);
}
void __init aruba_time_init(void)
{
unsigned int est_freq, flags;
local_irq_save(flags);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
est_freq = 2 * r4k_offset * HZ;
est_freq += 5000; /* round */
est_freq -= est_freq % 10000;
printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
(est_freq % 1000000) * 100 / 1000000);
local_irq_restore(flags);
}
void __init plat_timer_setup(struct irqaction *irq)
{
/* we are using the cpu counter for timer interrupts */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
/* to generate the first timer interrupt */
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
}
asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
{
int irq = MIPS_CPU_TIMER_IRQ;
irq_enter();
kstat_this_cpu.irqs[irq]++;
timer_interrupt(irq, NULL);
irq_exit();
}

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* PCI fixups for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/idt-boards/rc32434/rc32434.h>
#include <asm/idt-boards/rc32434/rc32434_pci.h>
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->bus->number != 0) {
return 0;
}
slot = PCI_SLOT(dev->devfn);
dev->irq = 0;
if (slot > 0 && slot <= 15) {
#if 1
if(slot == 10) {
if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 9; // intA
} else if(slot == 11) {
if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 10; // intA
if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 10; // intA
if(pin == 3) dev->irq = GROUP4_IRQ_BASE + 10; // intA
} else if(slot == 12) {
if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 11; // intA
if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 12; // intB
} else if (slot == 13) {
if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 12; // intA
if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 11; // intB
} else {
dev->irq = GROUP4_IRQ_BASE + 11;
}
#else
switch (pin) {
case 1: /* INTA*/
dev->irq = GROUP4_IRQ_BASE + 11;
break;
case 2: /* INTB */
dev->irq = GROUP4_IRQ_BASE + 11;
break;
case 3: /* INTC */
dev->irq = GROUP4_IRQ_BASE + 11;
break;
case 4: /* INTD */
dev->irq = GROUP4_IRQ_BASE + 11;
break;
default:
dev->irq = 0xff;
break;
}
#endif
#ifdef DEBUG
printk("irq fixup: slot %d, pin %d, irq %d\n",
slot, pin, dev->irq);
#endif
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
}
return (dev->irq);
}
struct pci_fixup pcibios_fixups[] = {
{0}
};

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* pci_ops for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/idt-boards/rc32434/rc32434.h>
#include <asm/idt-boards/rc32434/rc32434_pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define PCI_CFG_SET(slot,func,off) \
(rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
((func)<<8) | (off)))
static int config_access(unsigned char access_type, struct pci_bus *bus,
unsigned int devfn, unsigned char where,
u32 * data)
{
/*
* config cycles are on 4 byte boundary only
*/
unsigned int slot = PCI_SLOT(devfn);
u8 func = PCI_FUNC(devfn);
if (slot < 2 || slot > 15) {
*data = 0xFFFFFFFF;
return -1;
}
/* Setup address */
PCI_CFG_SET(slot, func, where);
rc32434_sync();
if (access_type == PCI_ACCESS_WRITE) {
rc32434_sync();
rc32434_pci->pcicfgd = *data;
} else {
rc32434_sync();
*data = rc32434_pci->pcicfgd;
}
rc32434_sync();
return 0;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 * val)
{
u32 data;
int ret;
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
*val = (data >> ((where & 3) << 3)) & 0xff;
return ret;
}
static int read_config_word(struct pci_bus *bus, unsigned int devfn,
int where, u16 * val)
{
u32 data;
int ret;
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
*val = (data >> ((where & 3) << 3)) & 0xffff;
return ret;
}
static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 * val)
{
int ret;
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
return ret;
}
static int
write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
u8 val)
{
u32 data = 0;
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
u16 val)
{
u32 data = 0;
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
u32 val)
{
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
switch (size) {
case 1:
return read_config_byte(bus, devfn, where, (u8 *) val);
case 2:
return read_config_word(bus, devfn, where, (u16 *) val);
default:
return read_config_dword(bus, devfn, where, val);
}
}
static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
switch (size) {
case 1:
return write_config_byte(bus, devfn, where, (u8) val);
case 2:
return write_config_word(bus, devfn, where, (u16) val);
default:
return write_config_dword(bus, devfn, where, val);
}
}
struct pci_ops rc32434_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* PCI initialization for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#include <linux/autoconf.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/idt-boards/rc32434/rc32434.h>
#include <asm/idt-boards/rc32434/rc32434_pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
/* define an unsigned array for the PCI registers */
unsigned int korinaCnfgRegs[25] = {
KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
};
static struct resource rc32434_res_pci_mem2;
static struct resource rc32434_res_pci_mem1 = {
.name = "PCI MEM1",
.start = 0x50000000,
.end = 0x5FFFFFFF,
.flags = IORESOURCE_MEM,
.child = &rc32434_res_pci_mem2,
};
static struct resource rc32434_res_pci_mem2 = {
.name = "PCI MEM2",
.start = 0x60000000,
.end = 0x6FFFFFFF,
.flags = IORESOURCE_MEM,
.parent = &rc32434_res_pci_mem1,
};
static struct resource rc32434_res_pci_io1 = {
.name = "PCI I/O1",
.start = 0x18800000,
.end = 0x188FFFFF,
.flags = IORESOURCE_IO,
};
extern struct pci_ops rc32434_pci_ops;
struct pci_controller rc32434_controller = {
.pci_ops = &rc32434_pci_ops,
.mem_resource = &rc32434_res_pci_mem1,
.io_resource = &rc32434_res_pci_io1,
.mem_offset = 0x00000000UL,
.io_offset = 0x00000000UL,
};
extern unsigned int arch_has_pci;
static int __init rc32434_pcibridge_init(void)
{
unsigned int pciConfigAddr = 0;/*used for writing pci config values */
int loopCount=0 ;/*used for the loop */
unsigned int pcicValue, pcicData=0;
unsigned int dummyRead, pciCntlVal = 0;
if (!arch_has_pci) return 0;
printk("PCI: Initializing PCI\n");
/* Disable the IP bus error for PCI scaning */
pciCntlVal=rc32434_pci->pcic;
pciCntlVal &= 0xFFFFFF7;
rc32434_pci->pcic = pciCntlVal;
ioport_resource.start = rc32434_res_pci_io1.start;
ioport_resource.end = rc32434_res_pci_io1.end;
/*
iomem_resource.start = rc32434_res_pci_mem1.start;
iomem_resource.end = rc32434_res_pci_mem1.end;
*/
pcicValue = rc32434_pci->pcic;
pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
if (!((pcicValue == PCIM_H_EA) ||
(pcicValue == PCIM_H_IA_FIX) ||
(pcicValue == PCIM_H_IA_RR))) {
/* Not in Host Mode, return ERROR */
return -1;
}
/* Enables the Idle Grant mode, Arbiter Parking */
pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
/* Zero out the PCI status & PCI Status Mask */
for(;;) {
pcicData = rc32434_pci->pcis;
if (!(pcicData & PCIS_rip_m))
break;
}
rc32434_pci->pcis = 0;
rc32434_pci->pcism = 0xFFFFFFFF;
/* Zero out the PCI decoupled registers */
rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
rc32434_pci->pcidas=0; /* clear the status */
rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
/* Mask PCI Messaging Interrupts */
rc32434_pci_msg->pciiic = 0;
rc32434_pci_msg->pciiim = 0xFFFFFFFF;
rc32434_pci_msg->pciioic = 0;
rc32434_pci_msg->pciioim = 0;
/* Setup PCILB0 as Memory Window */
rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
/* setup the PCI map address as same as the local address */
rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
/* Setup PCILBA1 as MEM */
#ifdef __MIPSEB__
rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
#else
rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
#endif
dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
rc32434_pci->pcilba[1].a = 0x60000000;
rc32434_pci->pcilba[1].m = 0x60000000;
/* setup PCILBA2 as IO Window*/
#ifdef __MIPSEB__
rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
#else
rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
#endif
dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
rc32434_pci->pcilba[2].a = 0x18C00000;
rc32434_pci->pcilba[2].m = 0x18FFFFFF;
/* setup PCILBA2 as IO Window*/
#ifdef __MIPSEB__
rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
#else
rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
#endif
dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
rc32434_pci->pcilba[3].a = 0x18800000;
rc32434_pci->pcilba[3].m = 0x18800000;
/* Setup PCILBA3 as IO Window */
#ifdef __MIPSEB__
rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCILBAC_sb_m);
#else
rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
#endif
dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
pciConfigAddr = (unsigned int)(0x80000004);
for(loopCount = 0; loopCount < 24; loopCount++){
rc32434_pci->pcicfga = pciConfigAddr;
dummyRead = rc32434_pci->pcicfga;
rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
dummyRead=rc32434_pci->pcicfgd;
pciConfigAddr += 4;
}
rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
pciCntlVal = rc32434_pci->pcic;
pciCntlVal &= ~(PCIC_tnr_m);
rc32434_pci->pcic = pciCntlVal;
pciCntlVal = rc32434_pci->pcic;
register_pci_controller(&rc32434_controller);
rc32434_sync();
return 0;
}
arch_initcall(rc32434_pcibridge_init);
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

110
target/linux/aruba-2.6/files/drivers/char/watchdog/wdt_merlot.c Normal file
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#include <linux/autoconf.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
extern unsigned long mips_machtype;
static unsigned long wdt_is_open;
static struct timer_list wdt_timer;
static void wdt_merlot_refresh(void)
{
volatile __u32 *wdt;
switch (mips_machtype) {
case MACH_ARUBA_AP70:
wdt = (__u32 *) 0xb8030034;
*wdt = 0x10000000;
break;
default:
wdt = (__u32 *) 0xbc00300c;
*wdt = 0x40000000;
break;
}
}
static void wdt_merlot_timer_fn(unsigned long data)
{
wdt_merlot_refresh();
if (!test_bit(1, &wdt_is_open))
mod_timer(&wdt_timer, jiffies + HZ);
}
static int wdt_merlot_setup_timer(void)
{
init_timer(&wdt_timer);
wdt_timer.function = wdt_merlot_timer_fn;
wdt_timer.data = 0;
wdt_timer.expires = jiffies + HZ;
add_timer(&wdt_timer);
return 0;
}
static int wdt_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
set_bit(1, &wdt_is_open);
return nonseekable_open(inode, file);
}
static ssize_t wdt_write(struct file *file, const char __user * buf, size_t count, loff_t * ppos)
{
if (count) /* something was written */
wdt_merlot_refresh();
return count;
}
static int wdt_release(struct inode *inode, struct file *file)
{
clear_bit(0, &wdt_is_open);
return 0;
}
static struct file_operations wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = wdt_write,
.open = wdt_open,
.release = wdt_release,
};
static struct miscdevice wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &wdt_fops,
};
static void __exit wdt_exit(void)
{
misc_deregister(&wdt_miscdev);
}
static int __init wdt_init(void)
{
int ret;
ret = misc_register(&wdt_miscdev);
if (ret) {
printk(KERN_ERR
"wdt: cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
misc_deregister(&wdt_miscdev);
goto out;
}
printk("wdt: registered with refresh\n");
wdt_merlot_refresh();
wdt_merlot_setup_timer();
out:
return ret;
}
module_init(wdt_init);
module_exit(wdt_exit);

5
target/linux/aruba-2.6/files/drivers/net/ar2313/Makefile Normal file
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#
# Makefile for the AR2313 ethernet driver
#
obj-$(CONFIG_AR2313) += ar2313.o

1649
target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.c Normal file
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190
target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313.h Normal file
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#ifndef _AR2313_H_
#define _AR2313_H_
#include <linux/autoconf.h>
#include <asm/bootinfo.h>
#include "platform.h"
extern unsigned long mips_machtype;
#undef ETHERNET_BASE
#define ETHERNET_BASE ar_eth_base
#define ETHERNET_SIZE 0x00100000
#define ETHERNET_MACS 2
#undef DMA_BASE
#define DMA_BASE ar_dma_base
#define DMA_SIZE 0x00100000
/*
* probe link timer - 5 secs
*/
#define LINK_TIMER (5*HZ)
/*
* Interrupt register base address
*/
#define INTERRUPT_BASE PHYS_TO_K1(ar_int_base)
/*
* Reset Register
*/
#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
#define RESET_SYSTEM 0x00000001 /* cold reset full system */
#define RESET_PROC 0x00000002 /* cold reset MIPS core */
#define RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
#define RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
#define RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
#define RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
#define RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
#ifndef K1_TO_PHYS
// hack
#define K1_TO_PHYS(x) (((unsigned int)(x)) & 0x1FFFFFFF) /* kseg1 to physical */
#endif
#ifndef PHYS_TO_K1
// hack
#define PHYS_TO_K1(x) (((unsigned int)(x)) | 0xA0000000) /* physical to kseg1 */
#endif
#define AR2313_TX_TIMEOUT (HZ/4)
/*
* Rings
*/
#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
static inline int tx_space (u32 csm, u32 prd)
{
return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1);
}
#if MAX_SKB_FRAGS
#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */
#define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED)
#else
#define tx_ring_full 0
#endif
#define AR2313_MBGET 2
#define AR2313_MBSET 3
#define AR2313_PCI_RECONFIG 4
#define AR2313_PCI_DUMP 5
#define AR2313_TEST_PANIC 6
#define AR2313_TEST_NULLPTR 7
#define AR2313_READ_DATA 8
#define AR2313_WRITE_DATA 9
#define AR2313_GET_VERSION 10
#define AR2313_TEST_HANG 11
#define AR2313_SYNC 12
struct ar2313_cmd {
u32 cmd;
u32 address; /* virtual address of image */
u32 length; /* size of image to download */
u32 mailbox; /* mailbox to get/set */
u32 data[2]; /* contents of mailbox to read/write */
};
/*
* Struct private for the Sibyte.
*
* Elements are grouped so variables used by the tx handling goes
* together, and will go into the same cache lines etc. in order to
* avoid cache line contention between the rx and tx handling on SMP.
*
* Frequently accessed variables are put at the beginning of the
* struct to help the compiler generate better/shorter code.
*/
struct ar2313_private
{
int version;
u32 mb[2];
volatile ETHERNET_STRUCT *eth_regs;
volatile DMA *dma_regs;
volatile u32 *int_regs;
spinlock_t lock; /* Serialise access to device */
/*
* RX and TX descriptors, must be adjacent
*/
ar2313_descr_t *rx_ring;
ar2313_descr_t *tx_ring;
struct sk_buff **rx_skb;
struct sk_buff **tx_skb;
/*
* RX elements
*/
u32 rx_skbprd;
u32 cur_rx;
/*
* TX elements
*/
u32 tx_prd;
u32 tx_csm;
/*
* Misc elements
*/
int board_idx;
char name[48];
struct net_device_stats stats;
struct {
u32 address;
u32 length;
char *mapping;
} desc;
struct timer_list link_timer;
unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
unsigned short mac;
unsigned short link; /* 0 - link down, 1 - link up */
u16 phyData;
struct tasklet_struct rx_tasklet;
int unloading;
};
/*
* Prototypes
*/
static int ar2313_init(struct net_device *dev);
#ifdef TX_TIMEOUT
static void ar2313_tx_timeout(struct net_device *dev);
#endif
#if 0
static void ar2313_multicast_list(struct net_device *dev);
#endif
static int ar2313_restart(struct net_device *dev);
#if DEBUG
static void ar2313_dump_regs(struct net_device *dev);
#endif
static void ar2313_load_rx_ring(struct net_device *dev, int bufs);
static irqreturn_t ar2313_interrupt(int irq, void *dev_id);
static int ar2313_open(struct net_device *dev);
static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev);
static int ar2313_close(struct net_device *dev);
static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
static void ar2313_init_cleanup(struct net_device *dev);
static int ar2313_setup_timer(struct net_device *dev);
static void ar2313_link_timer_fn(unsigned long data);
static void ar2313_check_link(struct net_device *dev);
static struct net_device_stats *ar2313_get_stats(struct net_device *dev);
#endif /* _AR2313_H_ */

17
target/linux/aruba-2.6/files/drivers/net/ar2313/ar2313_msg.h Normal file
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#ifndef _AR2313_MSG_H_
#define _AR2313_MSG_H_
#define AR2313_MTU 1692
#define AR2313_PRIOS 1
#define AR2313_QUEUES (2*AR2313_PRIOS)
#define AR2313_DESCR_ENTRIES 64
typedef struct {
volatile unsigned int status; // OWN, Device control and status.
volatile unsigned int devcs; // pkt Control bits + Length
volatile unsigned int addr; // Current Address.
volatile unsigned int descr; // Next descriptor in chain.
} ar2313_descr_t;
#endif /* _AR2313_MSG_H_ */

135
target/linux/aruba-2.6/files/drivers/net/ar2313/dma.h Normal file
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#ifndef __ARUBA_DMA_H__
#define __ARUBA_DMA_H__
/*******************************************************************************
*
* Copyright 2002 Integrated Device Technology, Inc.
* All rights reserved.
*
* DMA register definition.
*
* File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
*
* Author : ryan.holmQVist@idt.com
* Date : 20011005
* Update :
* $Log: dma.h,v $
* Revision 1.3 2002/06/06 18:34:03 astichte
* Added XXX_PhysicalAddress and XXX_VirtualAddress
*
* Revision 1.2 2002/06/05 18:30:46 astichte
* Removed IDTField
*
* Revision 1.1 2002/05/29 17:33:21 sysarch
* jba File moved from vcode/include/idt/acacia
*
*
******************************************************************************/
#define AR_BIT(x) (1 << (x))
#define DMA_RX_ERR_CRC AR_BIT(1)
#define DMA_RX_ERR_DRIB AR_BIT(2)
#define DMA_RX_ERR_MII AR_BIT(3)
#define DMA_RX_EV2 AR_BIT(5)
#define DMA_RX_ERR_COL AR_BIT(6)
#define DMA_RX_LONG AR_BIT(7)
#define DMA_RX_LS AR_BIT(8) /* last descriptor */
#define DMA_RX_FS AR_BIT(9) /* first descriptor */
#define DMA_RX_MF AR_BIT(10) /* multicast frame */
#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
#define DMA_RX_ERROR AR_BIT(15) /* error summary */
#define DMA_RX_LEN_MASK 0x3fff0000
#define DMA_RX_LEN_SHIFT 16
#define DMA_RX_FILT AR_BIT(30)
#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
#define DMA_RX1_BSIZE_MASK 0x000007ff
#define DMA_RX1_BSIZE_SHIFT 0
#define DMA_RX1_CHAINED AR_BIT(24)
#define DMA_RX1_RER AR_BIT(25)
#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
#define DMA_TX_COL_MASK 0x78
#define DMA_TX_COL_SHIFT 3
#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
#define DMA_TX1_BSIZE_MASK 0x000007ff
#define DMA_TX1_BSIZE_SHIFT 0
#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
#define DMA_TX1_FS AR_BIT(29) /* first segment */
#define DMA_TX1_LS AR_BIT(30) /* last segment */
#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check*/
#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames only) */
#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE SET) */
#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid frames) */
#define MII_ADDR_BUSY AR_BIT(0)
#define MII_ADDR_WRITE AR_BIT(1)
#define MII_ADDR_REG_SHIFT 6
#define MII_ADDR_PHY_SHIFT 11
#define MII_DATA_SHIFT 0
#define FLOW_CONTROL_FCE AR_BIT(1)
#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
#define DMA_STATUS_EB_SHIFT 23 /* error bits */
#define DMA_CONTROL_SR AR_BIT(1) /* start receive */
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
#endif // __ARUBA_DMA_H__

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/********************************************************************************
Title: $Source: platform.h,v $
Author: Dan Steinberg
Copyright Integrated Device Technology 2001
Purpose: AR2313 Register/Bit Definitions
Update:
$Log: platform.h,v $
Notes: See Merlot architecture spec for complete details. Note, all
addresses are virtual addresses in kseg1 (Uncached, Unmapped).
********************************************************************************/
#ifndef PLATFORM_H
#define PLATFORM_H
#define BIT(x) (1 << (x))
#define RESET_BASE 0xBC003020
#define RESET_VALUE 0x00000001
/********************************************************************
* Device controller
********************************************************************/
typedef struct {
volatile unsigned int flash0;
} DEVICE;
#define device (*((volatile DEVICE *) DEV_CTL_BASE))
// DDRC register
#define DEV_WP (1<<26)
/********************************************************************
* DDR controller
********************************************************************/
typedef struct {
volatile unsigned int ddrc0;
volatile unsigned int ddrc1;
volatile unsigned int ddrrefresh;
} DDR;
#define ddr (*((volatile DDR *) DDR_BASE))
// DDRC register
#define DDRC_CS(i) ((i&0x3)<<0)
#define DDRC_WE (1<<2)
/********************************************************************
* Ethernet interfaces
********************************************************************/
#define ETHERNET_BASE 0xB8200000
//
// New Combo structure for Both Eth0 AND eth1
//
typedef struct {
volatile unsigned int mac_control; /* 0x00 */
volatile unsigned int mac_addr[2]; /* 0x04 - 0x08*/
volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
volatile unsigned int mii_addr; /* 0x14 */
volatile unsigned int mii_data; /* 0x18 */
volatile unsigned int flow_control; /* 0x1c */
volatile unsigned int vlan_tag; /* 0x20 */
volatile unsigned int pad[7]; /* 0x24 - 0x3c */
volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
} ETHERNET_STRUCT;
/********************************************************************
* Interrupt controller
********************************************************************/
typedef struct {
volatile unsigned int wdog_control; /* 0x08 */
volatile unsigned int wdog_timer; /* 0x0c */
volatile unsigned int misc_status; /* 0x10 */
volatile unsigned int misc_mask; /* 0x14 */
volatile unsigned int global_status; /* 0x18 */
volatile unsigned int reserved; /* 0x1c */
volatile unsigned int reset_control; /* 0x20 */
} INTERRUPT;
#define interrupt (*((volatile INTERRUPT *) INTERRUPT_BASE))
#define INTERRUPT_MISC_TIMER BIT(0)
#define INTERRUPT_MISC_AHBPROC BIT(1)
#define INTERRUPT_MISC_AHBDMA BIT(2)
#define INTERRUPT_MISC_GPIO BIT(3)
#define INTERRUPT_MISC_UART BIT(4)
#define INTERRUPT_MISC_UARTDMA BIT(5)
#define INTERRUPT_MISC_WATCHDOG BIT(6)
#define INTERRUPT_MISC_LOCAL BIT(7)
#define INTERRUPT_GLOBAL_ETH BIT(2)
#define INTERRUPT_GLOBAL_WLAN BIT(3)
#define INTERRUPT_GLOBAL_MISC BIT(4)
#define INTERRUPT_GLOBAL_ITIMER BIT(5)
/********************************************************************
* DMA controller
********************************************************************/
#define DMA_BASE 0xB8201000
typedef struct {
volatile unsigned int bus_mode; /* 0x00 (CSR0) */
volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
volatile unsigned int rcv_base; /* 0x0c (CSR3) */
volatile unsigned int xmt_base; /* 0x10 (CSR4) */
volatile unsigned int status; /* 0x14 (CSR5) */
volatile unsigned int control; /* 0x18 (CSR6) */
volatile unsigned int intr_ena; /* 0x1c (CSR7) */
volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
} DMA;
#define dma (*((volatile DMA *) DMA_BASE))
// macro to convert from virtual to physical address
#define phys_addr(x) (x & 0x1fffffff)
#endif /* PLATFORM_H */

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Definitions for IDT RC32434 on-chip ethernet controller.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
* Aug 2004
*
* Added NAPI
*
**************************************************************************
*/
#include <asm/idt-boards/rc32434/rc32434.h>
#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
#define RC32434_DEBUG 2
//#define RC32434_PROC_DEBUG
#undef RC32434_DEBUG
#ifdef RC32434_DEBUG
/* use 0 for production, 1 for verification, >2 for debug */
static int rc32434_debug = RC32434_DEBUG;
#define ASSERT(expr) \
if(!(expr)) { \
printk( "Assertion failed! %s,%s,%s,line=%d\n", \
#expr,__FILE__,__FUNCTION__,__LINE__); }
#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
#else
#define ASSERT(expr) do {} while (0)
#define DBG(lvl, format, arg...) do {} while (0)
#endif
#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
/* the following must be powers of two */
#ifdef CONFIG_IDT_USE_NAPI
#define RC32434_NUM_RDS 64 /* number of receive descriptors */
#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
#else
#define RC32434_NUM_RDS 128 /* number of receive descriptors */
#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
#endif
#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
#define RC32434_TX_TIMEOUT HZ * 100
#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
enum status { filled, empty};
#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
/* Information that need to be kept for each board. */
struct rc32434_local {
ETH_t eth_regs;
DMA_Chan_t rx_dma_regs;
DMA_Chan_t tx_dma_regs;
volatile DMAD_t td_ring; /* transmit descriptor ring */
volatile DMAD_t rd_ring; /* receive descriptor ring */
struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
#ifndef CONFIG_IDT_USE_NAPI
struct tasklet_struct * rx_tasklet;
#endif
struct tasklet_struct * tx_tasklet;
int rx_next_done;
int rx_chain_head;
int rx_chain_tail;
enum status rx_chain_status;
int tx_next_done;
int tx_chain_head;
int tx_chain_tail;
enum status tx_chain_status;
int tx_count;
int tx_full;
struct timer_list mii_phy_timer;
unsigned long duplex_mode;
int rx_irq;
int tx_irq;
int ovr_irq;
int und_irq;
struct net_device_stats stats;
spinlock_t lock;
/* debug /proc entry */
struct proc_dir_entry *ps;
int dma_halt_cnt; int dma_run_cnt;
};
extern unsigned int idt_cpu_freq;
/* Index to functions, as function prototypes. */
static int rc32434_open(struct net_device *dev);
static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
static void rc32434_mii_handler(unsigned long data);
static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id);
static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id);
static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id);
#ifdef RC32434_REVISION
static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id);
#endif
static int rc32434_close(struct net_device *dev);
static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
static void rc32434_multicast_list(struct net_device *dev);
static int rc32434_init(struct net_device *dev);
static void rc32434_tx_timeout(struct net_device *dev);
static void rc32434_tx_tasklet(unsigned long tx_data_dev);
#ifdef CONFIG_IDT_USE_NAPI
static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
#else
static void rc32434_rx_tasklet(unsigned long rx_data_dev);
#endif
static void rc32434_cleanup_module(void);
static int rc32434_probe(int port_num);
int rc32434_init_module(void);
static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
{
if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
rc32434_writel(0x10, &ch->dmac);
while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
dev->trans_start = jiffies;
rc32434_writel(0, &ch->dmas);
}
rc32434_writel(0, &ch->dmadptr);
rc32434_writel(0, &ch->dmandptr);
}

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Definitions for IDT RC32434 CPU
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef _RC32434_H_
#define _RC32434_H_
#include <linux/autoconf.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/idt-boards/rc32434/rc32434_timer.h>
#define RC32434_REG_BASE 0x18000000
#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
#define IDT_CLOCK_MULT 2
#define MIPS_CPU_TIMER_IRQ 7
/* Interrupt Controller */
#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
#define IC_GROUP_OFFSET 0x0C
#define RTC_BASE 0xBA001FF0
#define NUM_INTR_GROUPS 5
/* 16550 UARTs */
#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
#ifdef __MIPSEB__
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
#define EB434_UART1_BASE (0x19800003)
#else
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
#define EB434_UART1_BASE (0x19800000)
#endif
#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
/* cpu pipeline flush */
static inline void rc32434_sync(void)
{
__asm__ volatile ("sync");
}
static inline void rc32434_sync_udelay(int us)
{
__asm__ volatile ("sync");
udelay(us);
}
static inline void rc32434_sync_delay(int ms)
{
__asm__ volatile ("sync");
mdelay(ms);
}
/*
* Macros to access internal RC32434 registers. No byte
* swapping should be done when accessing the internal
* registers.
*/
#define rc32434_readb __raw_readb
#define rc32434_readw __raw_readw
#define rc32434_readl __raw_readl
#define rc32434_writeb __raw_writeb
#define rc32434_writew __raw_writew
#define rc32434_writel __raw_writel
#if 0
static inline u8 rc32434_readb(unsigned long pa)
{
return *((volatile u8 *)KSEG1ADDR(pa));
}
static inline u16 rc32434_readw(unsigned long pa)
{
return *((volatile u16 *)KSEG1ADDR(pa));
}
static inline u32 rc32434_readl(unsigned long pa)
{
return *((volatile u32 *)KSEG1ADDR(pa));
}
static inline void rc32434_writeb(u8 val, unsigned long pa)
{
*((volatile u8 *)KSEG1ADDR(pa)) = val;
}
static inline void rc32434_writew(u16 val, unsigned long pa)
{
*((volatile u16 *)KSEG1ADDR(pa)) = val;
}
static inline void rc32434_writel(u32 val, unsigned long pa)
{
*((volatile u32 *)KSEG1ADDR(pa)) = val;
}
#endif
/*
* C access to CLZ and CLO instructions
* (count leading zeroes/ones).
*/
static inline int rc32434_clz(unsigned long val)
{
int ret;
__asm__ volatile (
".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips32\n\t"
"clz\t%0,%1\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (ret)
: "r" (val));
return ret;
}
static inline int rc32434_clo(unsigned long val)
{
int ret;
__asm__ volatile (
".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips32\n\t"
"clo\t%0,%1\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
: "=r" (ret)
: "r" (val));
return ret;
}
#endif /* _RC32434_H_ */

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* DMA register definition
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_DMA_H__
#define __IDT_DMA_H__
enum
{
DMA0_PhysicalAddress = 0x18040000,
DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
DMA0_VirtualAddress = 0xb8040000,
DMA_VirtualAddress = DMA0_VirtualAddress, // Default
} ;
/*
* DMA descriptor (in physical memory).
*/
typedef struct DMAD_s
{
u32 control ; // Control. use DMAD_*
u32 ca ; // Current Address.
u32 devcs ; // Device control and status.
u32 link ; // Next descriptor in chain.
} volatile *DMAD_t ;
enum
{
DMAD_size = sizeof (struct DMAD_s),
DMAD_count_b = 0, // in DMAD_t -> control
DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
DMAD_ds_b = 20, // in DMAD_t -> control
DMAD_ds_m = 0x00300000, // in DMAD_t -> control
DMAD_ds_ethRcv0_v = 0,
DMAD_ds_ethXmt0_v = 0,
DMAD_ds_memToFifo_v = 0,
DMAD_ds_fifoToMem_v = 0,
DMAD_ds_pciToMem_v = 0,
DMAD_ds_memToPci_v = 0,
DMAD_devcmd_b = 22, // in DMAD_t -> control
DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
DMAD_devcmd_byte_v = 0, //memory-to-memory
DMAD_devcmd_halfword_v = 1, //memory-to-memory
DMAD_devcmd_word_v = 2, //memory-to-memory
DMAD_devcmd_2words_v = 3, //memory-to-memory
DMAD_devcmd_4words_v = 4, //memory-to-memory
DMAD_devcmd_6words_v = 5, //memory-to-memory
DMAD_devcmd_8words_v = 6, //memory-to-memory
DMAD_devcmd_16words_v = 7, //memory-to-memory
DMAD_cof_b = 25, // chain on finished
DMAD_cof_m = 0x02000000, //
DMAD_cod_b = 26, // chain on done
DMAD_cod_m = 0x04000000, //
DMAD_iof_b = 27, // interrupt on finished
DMAD_iof_m = 0x08000000, //
DMAD_iod_b = 28, // interrupt on done
DMAD_iod_m = 0x10000000, //
DMAD_t_b = 29, // terminated
DMAD_t_m = 0x20000000, //
DMAD_d_b = 30, // done
DMAD_d_m = 0x40000000, //
DMAD_f_b = 31, // finished
DMAD_f_m = 0x80000000, //
} ;
/*
* DMA register (within Internal Register Map).
*/
struct DMA_Chan_s
{
u32 dmac ; // Control.
u32 dmas ; // Status.
u32 dmasm ; // Mask.
u32 dmadptr ; // Descriptor pointer.
u32 dmandptr ; // Next descriptor pointer.
};
typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
//DMA_Channels use DMACH_count instead
enum
{
DMAC_run_b = 0, //
DMAC_run_m = 0x00000001, //
DMAC_dm_b = 1, // done mask
DMAC_dm_m = 0x00000002, //
DMAC_mode_b = 2, //
DMAC_mode_m = 0x0000000c, //
DMAC_mode_auto_v = 0,
DMAC_mode_burst_v = 1,
DMAC_mode_transfer_v = 2, //usually used
DMAC_mode_reserved_v = 3,
DMAC_a_b = 4, //
DMAC_a_m = 0x00000010, //
DMAS_f_b = 0, // finished (sticky)
DMAS_f_m = 0x00000001, //
DMAS_d_b = 1, // done (sticky)
DMAS_d_m = 0x00000002, //
DMAS_c_b = 2, // chain (sticky)
DMAS_c_m = 0x00000004, //
DMAS_e_b = 3, // error (sticky)
DMAS_e_m = 0x00000008, //
DMAS_h_b = 4, // halt (sticky)
DMAS_h_m = 0x00000010, //
DMASM_f_b = 0, // finished (1=mask)
DMASM_f_m = 0x00000001, //
DMASM_d_b = 1, // done (1=mask)
DMASM_d_m = 0x00000002, //
DMASM_c_b = 2, // chain (1=mask)
DMASM_c_m = 0x00000004, //
DMASM_e_b = 3, // error (1=mask)
DMASM_e_m = 0x00000008, //
DMASM_h_b = 4, // halt (1=mask)
DMASM_h_m = 0x00000010, //
} ;
/*
* DMA channel definitions
*/
enum
{
DMACH_ethRcv0 = 0,
DMACH_ethXmt0 = 1,
DMACH_memToFifo = 2,
DMACH_fifoToMem = 3,
DMACH_pciToMem = 4,
DMACH_memToPci = 5,
DMACH_count //must be last
};
typedef struct DMAC_s
{
struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
} volatile *DMA_t ;
/*
* External DMA parameters
*/
enum
{
DMADEVCMD_ts_b = 0, // ts field in devcmd
DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
DMADEVCMD_ts_byte_v = 0,
DMADEVCMD_ts_halfword_v = 1,
DMADEVCMD_ts_word_v = 2,
DMADEVCMD_ts_2word_v = 3,
DMADEVCMD_ts_4word_v = 4,
DMADEVCMD_ts_6word_v = 5,
DMADEVCMD_ts_8word_v = 6,
DMADEVCMD_ts_16word_v = 7
};
#endif // __IDT_DMA_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Definitions for DMA controller.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_DMA_V_H__
#define __IDT_DMA_V_H__
#include <asm/idt-boards/rc32434/rc32434_dma.h>
#include <asm/idt-boards/rc32434/rc32434.h>
#define DMA_CHAN_OFFSET 0x14
#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
#define DMA_COUNT(count) \
((count) & DMAD_count_m)
#define DMA_HALT_TIMEOUT 500
static inline int rc32434_halt_dma(DMA_Chan_t ch)
{
int timeout=1;
if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
rc32434_writel(0, &ch->dmac);
for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
rc32434_writel(0, &ch->dmas);
break;
}
}
}
return timeout ? 0 : 1;
}
static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
{
rc32434_writel(0, &ch->dmandptr);
rc32434_writel(dma_addr, &ch->dmadptr);
}
static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
{
rc32434_writel(dma_addr, &ch->dmandptr);
}
#endif // __IDT_DMA_V_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Ethernet register definition
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_ETH_H__
#define __IDT_ETH_H__
enum
{
ETH0_PhysicalAddress = 0x18060000,
ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
ETH0_VirtualAddress = 0xb8060000,
ETH_VirtualAddress = ETH0_VirtualAddress, // Default
} ;
typedef struct
{
u32 ethintfc ;
u32 ethfifott ;
u32 etharc ;
u32 ethhash0 ;
u32 ethhash1 ;
u32 ethu0 [4] ; // Reserved.
u32 ethpfs ;
u32 ethmcp ;
u32 eth_u1 [10] ; // Reserved.
u32 ethspare ;
u32 eth_u2 [42] ; // Reserved.
u32 ethsal0 ;
u32 ethsah0 ;
u32 ethsal1 ;
u32 ethsah1 ;
u32 ethsal2 ;
u32 ethsah2 ;
u32 ethsal3 ;
u32 ethsah3 ;
u32 ethrbc ;
u32 ethrpc ;
u32 ethrupc ;
u32 ethrfc ;
u32 ethtbc ;
u32 ethgpf ;
u32 eth_u9 [50] ; // Reserved.
u32 ethmac1 ;
u32 ethmac2 ;
u32 ethipgt ;
u32 ethipgr ;
u32 ethclrt ;
u32 ethmaxf ;
u32 eth_u10 ; // Reserved.
u32 ethmtest ;
u32 miimcfg ;
u32 miimcmd ;
u32 miimaddr ;
u32 miimwtd ;
u32 miimrdd ;
u32 miimind ;
u32 eth_u11 ; // Reserved.
u32 eth_u12 ; // Reserved.
u32 ethcfsa0 ;
u32 ethcfsa1 ;
u32 ethcfsa2 ;
} volatile *ETH_t;
enum
{
ETHINTFC_en_b = 0,
ETHINTFC_en_m = 0x00000001,
ETHINTFC_its_b = 1,
ETHINTFC_its_m = 0x00000002,
ETHINTFC_rip_b = 2,
ETHINTFC_rip_m = 0x00000004,
ETHINTFC_jam_b = 3,
ETHINTFC_jam_m = 0x00000008,
ETHINTFC_ovr_b = 4,
ETHINTFC_ovr_m = 0x00000010,
ETHINTFC_und_b = 5,
ETHINTFC_und_m = 0x00000020,
ETHFIFOTT_tth_b = 0,
ETHFIFOTT_tth_m = 0x0000007f,
ETHARC_pro_b = 0,
ETHARC_pro_m = 0x00000001,
ETHARC_am_b = 1,
ETHARC_am_m = 0x00000002,
ETHARC_afm_b = 2,
ETHARC_afm_m = 0x00000004,
ETHARC_ab_b = 3,
ETHARC_ab_m = 0x00000008,
ETHSAL_byte5_b = 0,
ETHSAL_byte5_m = 0x000000ff,
ETHSAL_byte4_b = 8,
ETHSAL_byte4_m = 0x0000ff00,
ETHSAL_byte3_b = 16,
ETHSAL_byte3_m = 0x00ff0000,
ETHSAL_byte2_b = 24,
ETHSAL_byte2_m = 0xff000000,
ETHSAH_byte1_b = 0,
ETHSAH_byte1_m = 0x000000ff,
ETHSAH_byte0_b = 8,
ETHSAH_byte0_m = 0x0000ff00,
ETHGPF_ptv_b = 0,
ETHGPF_ptv_m = 0x0000ffff,
ETHPFS_pfd_b = 0,
ETHPFS_pfd_m = 0x00000001,
ETHCFSA0_cfsa4_b = 0,
ETHCFSA0_cfsa4_m = 0x000000ff,
ETHCFSA0_cfsa5_b = 8,
ETHCFSA0_cfsa5_m = 0x0000ff00,
ETHCFSA1_cfsa2_b = 0,
ETHCFSA1_cfsa2_m = 0x000000ff,
ETHCFSA1_cfsa3_b = 8,
ETHCFSA1_cfsa3_m = 0x0000ff00,
ETHCFSA2_cfsa0_b = 0,
ETHCFSA2_cfsa0_m = 0x000000ff,
ETHCFSA2_cfsa1_b = 8,
ETHCFSA2_cfsa1_m = 0x0000ff00,
ETHMAC1_re_b = 0,
ETHMAC1_re_m = 0x00000001,
ETHMAC1_paf_b = 1,
ETHMAC1_paf_m = 0x00000002,
ETHMAC1_rfc_b = 2,
ETHMAC1_rfc_m = 0x00000004,
ETHMAC1_tfc_b = 3,
ETHMAC1_tfc_m = 0x00000008,
ETHMAC1_lb_b = 4,
ETHMAC1_lb_m = 0x00000010,
ETHMAC1_mr_b = 31,
ETHMAC1_mr_m = 0x80000000,
ETHMAC2_fd_b = 0,
ETHMAC2_fd_m = 0x00000001,
ETHMAC2_flc_b = 1,
ETHMAC2_flc_m = 0x00000002,
ETHMAC2_hfe_b = 2,
ETHMAC2_hfe_m = 0x00000004,
ETHMAC2_dc_b = 3,
ETHMAC2_dc_m = 0x00000008,
ETHMAC2_cen_b = 4,
ETHMAC2_cen_m = 0x00000010,
ETHMAC2_pe_b = 5,
ETHMAC2_pe_m = 0x00000020,
ETHMAC2_vpe_b = 6,
ETHMAC2_vpe_m = 0x00000040,
ETHMAC2_ape_b = 7,
ETHMAC2_ape_m = 0x00000080,
ETHMAC2_ppe_b = 8,
ETHMAC2_ppe_m = 0x00000100,
ETHMAC2_lpe_b = 9,
ETHMAC2_lpe_m = 0x00000200,
ETHMAC2_nb_b = 12,
ETHMAC2_nb_m = 0x00001000,
ETHMAC2_bp_b = 13,
ETHMAC2_bp_m = 0x00002000,
ETHMAC2_ed_b = 14,
ETHMAC2_ed_m = 0x00004000,
ETHIPGT_ipgt_b = 0,
ETHIPGT_ipgt_m = 0x0000007f,
ETHIPGR_ipgr2_b = 0,
ETHIPGR_ipgr2_m = 0x0000007f,
ETHIPGR_ipgr1_b = 8,
ETHIPGR_ipgr1_m = 0x00007f00,
ETHCLRT_maxret_b = 0,
ETHCLRT_maxret_m = 0x0000000f,
ETHCLRT_colwin_b = 8,
ETHCLRT_colwin_m = 0x00003f00,
ETHMAXF_maxf_b = 0,
ETHMAXF_maxf_m = 0x0000ffff,
ETHMTEST_tb_b = 2,
ETHMTEST_tb_m = 0x00000004,
ETHMCP_div_b = 0,
ETHMCP_div_m = 0x000000ff,
MIIMCFG_rsv_b = 0,
MIIMCFG_rsv_m = 0x0000000c,
MIIMCMD_rd_b = 0,
MIIMCMD_rd_m = 0x00000001,
MIIMCMD_scn_b = 1,
MIIMCMD_scn_m = 0x00000002,
MIIMADDR_regaddr_b = 0,
MIIMADDR_regaddr_m = 0x0000001f,
MIIMADDR_phyaddr_b = 8,
MIIMADDR_phyaddr_m = 0x00001f00,
MIIMWTD_wdata_b = 0,
MIIMWTD_wdata_m = 0x0000ffff,
MIIMRDD_rdata_b = 0,
MIIMRDD_rdata_m = 0x0000ffff,
MIIMIND_bsy_b = 0,
MIIMIND_bsy_m = 0x00000001,
MIIMIND_scn_b = 1,
MIIMIND_scn_m = 0x00000002,
MIIMIND_nv_b = 2,
MIIMIND_nv_m = 0x00000004,
} ;
/*
* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
*/
enum
{
ETHRX_fd_b = 0,
ETHRX_fd_m = 0x00000001,
ETHRX_ld_b = 1,
ETHRX_ld_m = 0x00000002,
ETHRX_rok_b = 2,
ETHRX_rok_m = 0x00000004,
ETHRX_fm_b = 3,
ETHRX_fm_m = 0x00000008,
ETHRX_mp_b = 4,
ETHRX_mp_m = 0x00000010,
ETHRX_bp_b = 5,
ETHRX_bp_m = 0x00000020,
ETHRX_vlt_b = 6,
ETHRX_vlt_m = 0x00000040,
ETHRX_cf_b = 7,
ETHRX_cf_m = 0x00000080,
ETHRX_ovr_b = 8,
ETHRX_ovr_m = 0x00000100,
ETHRX_crc_b = 9,
ETHRX_crc_m = 0x00000200,
ETHRX_cv_b = 10,
ETHRX_cv_m = 0x00000400,
ETHRX_db_b = 11,
ETHRX_db_m = 0x00000800,
ETHRX_le_b = 12,
ETHRX_le_m = 0x00001000,
ETHRX_lor_b = 13,
ETHRX_lor_m = 0x00002000,
ETHRX_ces_b = 14,
ETHRX_ces_m = 0x00004000,
ETHRX_length_b = 16,
ETHRX_length_m = 0xffff0000,
ETHTX_fd_b = 0,
ETHTX_fd_m = 0x00000001,
ETHTX_ld_b = 1,
ETHTX_ld_m = 0x00000002,
ETHTX_oen_b = 2,
ETHTX_oen_m = 0x00000004,
ETHTX_pen_b = 3,
ETHTX_pen_m = 0x00000008,
ETHTX_cen_b = 4,
ETHTX_cen_m = 0x00000010,
ETHTX_hen_b = 5,
ETHTX_hen_m = 0x00000020,
ETHTX_tok_b = 6,
ETHTX_tok_m = 0x00000040,
ETHTX_mp_b = 7,
ETHTX_mp_m = 0x00000080,
ETHTX_bp_b = 8,
ETHTX_bp_m = 0x00000100,
ETHTX_und_b = 9,
ETHTX_und_m = 0x00000200,
ETHTX_of_b = 10,
ETHTX_of_m = 0x00000400,
ETHTX_ed_b = 11,
ETHTX_ed_m = 0x00000800,
ETHTX_ec_b = 12,
ETHTX_ec_m = 0x00001000,
ETHTX_lc_b = 13,
ETHTX_lc_m = 0x00002000,
ETHTX_td_b = 14,
ETHTX_td_m = 0x00004000,
ETHTX_crc_b = 15,
ETHTX_crc_m = 0x00008000,
ETHTX_le_b = 16,
ETHTX_le_m = 0x00010000,
ETHTX_cc_b = 17,
ETHTX_cc_m = 0x001E0000,
} ;
#endif // __IDT_ETH_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Ethernet register definition
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_ETH_V_H__
#define __IDT_ETH_V_H__
#include <asm/idt-boards/rc32434/rc32434_eth.h>
#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
#endif // __IDT_ETH_V_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* GPIO register definition
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_GPIO_H__
#define __IDT_GPIO_H__
enum
{
GPIO0_PhysicalAddress = 0x18050000,
GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
GPIO0_VirtualAddress = 0xb8050000,
GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
} ;
typedef struct
{
u32 gpiofunc; /* GPIO Function Register
* gpiofunc[x]==0 bit = gpio
* func[x]==1 bit = altfunc
*/
u32 gpiocfg; /* GPIO Configuration Register
* gpiocfg[x]==0 bit = input
* gpiocfg[x]==1 bit = output
*/
u32 gpiod; /* GPIO Data Register
* gpiod[x] read/write gpio pinX status
*/
u32 gpioilevel; /* GPIO Interrupt Status Register
* interrupt level (see gpioistat)
*/
u32 gpioistat; /* Gpio Interrupt Status Register
* istat[x] = (gpiod[x] == level[x])
* cleared in ISR (STICKY bits)
*/
u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
} volatile * GPIO_t ;
typedef enum
{
GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
GPIO_alt_v = 1, // gpiofunc use pin as alt.
GPIO_input_v = 0, // gpiocfg use pin as input.
GPIO_output_v = 1, // gpiocfg use pin as output.
GPIO_pin0_b = 0,
GPIO_pin0_m = 0x00000001,
GPIO_pin1_b = 1,
GPIO_pin1_m = 0x00000002,
GPIO_pin2_b = 2,
GPIO_pin2_m = 0x00000004,
GPIO_pin3_b = 3,
GPIO_pin3_m = 0x00000008,
GPIO_pin4_b = 4,
GPIO_pin4_m = 0x00000010,
GPIO_pin5_b = 5,
GPIO_pin5_m = 0x00000020,
GPIO_pin6_b = 6,
GPIO_pin6_m = 0x00000040,
GPIO_pin7_b = 7,
GPIO_pin7_m = 0x00000080,
GPIO_pin8_b = 8,
GPIO_pin8_m = 0x00000100,
GPIO_pin9_b = 9,
GPIO_pin9_m = 0x00000200,
GPIO_pin10_b = 10,
GPIO_pin10_m = 0x00000400,
GPIO_pin11_b = 11,
GPIO_pin11_m = 0x00000800,
GPIO_pin12_b = 12,
GPIO_pin12_m = 0x00001000,
GPIO_pin13_b = 13,
GPIO_pin13_m = 0x00002000,
// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
GPIO_u0sout_m = GPIO_pin0_m,
GPIO_u0sout_cfg_v = GPIO_output_v,
GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
GPIO_u0sinp_m = GPIO_pin1_m,
GPIO_u0sinp_cfg_v = GPIO_input_v,
GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
GPIO_u0rtsn_m = GPIO_pin2_m,
GPIO_u0rtsn_cfg_v = GPIO_output_v,
GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
GPIO_u0ctsn_m = GPIO_pin3_m,
GPIO_u0ctsn_cfg_v = GPIO_input_v,
GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
GPIO_maddr22_m = GPIO_pin4_m,
GPIO_maddr22_cfg_v = GPIO_output_v,
GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
GPIO_maddr23_m = GPIO_pin5_m,
GPIO_maddr23_cfg_v = GPIO_output_v,
GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
GPIO_maddr24_m = GPIO_pin6_m,
GPIO_maddr24_cfg_v = GPIO_output_v,
GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
GPIO_maddr25_m = GPIO_pin7_m,
GPIO_maddr25_cfg_v = GPIO_output_v,
GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
GPIO_cpudmadebug_m = GPIO_pin8_m,
GPIO_cpudmadebug_cfg_v = GPIO_output_v,
GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
GPIO_pcireq4_m = GPIO_pin9_m,
GPIO_pcireq4_cfg_v = GPIO_input_v,
GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
GPIO_pcigrant4_m = GPIO_pin10_m,
GPIO_pcigrant4_cfg_v = GPIO_output_v,
GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
GPIO_pcireq5_m = GPIO_pin11_m,
GPIO_pcireq5_cfg_v = GPIO_input_v,
GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
GPIO_pcigrant5_m = GPIO_pin12_m,
GPIO_pcigrant5_cfg_v = GPIO_output_v,
GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
GPIO_pcimuintn_m = GPIO_pin13_m,
GPIO_pcimuintn_cfg_v = GPIO_output_v,
} GPIO_DEFS_t;
#endif // __IDT_GPIO_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Interrupt Controller register definition.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_INT_H__
#define __IDT_INT_H__
enum
{
INT0_PhysicalAddress = 0x18038000,
INT_PhysicalAddress = INT0_PhysicalAddress, // Default
INT0_VirtualAddress = 0xB8038000,
INT_VirtualAddress = INT0_VirtualAddress, // Default
} ;
struct INT_s
{
u32 ipend ; //Pending interrupts. use INT?_
u32 itest ; //Test bits. use INT?_
u32 imask ; //Interrupt disabled when set. use INT?_
} ;
enum
{
IPEND2 = 0, // HW 2 interrupt to core. use INT2_
IPEND3 = 1, // HW 3 interrupt to core. use INT3_
IPEND4 = 2, // HW 4 interrupt to core. use INT4_
IPEND5 = 3, // HW 5 interrupt to core. use INT5_
IPEND6 = 4, // HW 6 interrupt to core. use INT6_
IPEND_count, // must be last (used in loops)
IPEND_min = IPEND2 // min IPEND (used in loops)
};
typedef struct INTC_s
{
struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
u32 nmips ; // use NMIPS_
} volatile *INT_t ;
enum
{
INT2_timer0_b = 0,
INT2_timer0_m = 0x00000001,
INT2_timer1_b = 1,
INT2_timer1_m = 0x00000002,
INT2_timer2_b = 2,
INT2_timer2_m = 0x00000004,
INT2_refresh_b = 3,
INT2_refresh_m = 0x00000008,
INT2_watchdogTimeout_b = 4,
INT2_watchdogTimeout_m = 0x00000010,
INT2_undecodedCpuWrite_b = 5,
INT2_undecodedCpuWrite_m = 0x00000020,
INT2_undecodedCpuRead_b = 6,
INT2_undecodedCpuRead_m = 0x00000040,
INT2_undecodedPciWrite_b = 7,
INT2_undecodedPciWrite_m = 0x00000080,
INT2_undecodedPciRead_b = 8,
INT2_undecodedPciRead_m = 0x00000100,
INT2_undecodedDmaWrite_b = 9,
INT2_undecodedDmaWrite_m = 0x00000200,
INT2_undecodedDmaRead_b = 10,
INT2_undecodedDmaRead_m = 0x00000400,
INT2_ipBusSlaveAckError_b = 11,
INT2_ipBusSlaveAckError_m = 0x00000800,
INT3_dmaChannel0_b = 0,
INT3_dmaChannel0_m = 0x00000001,
INT3_dmaChannel1_b = 1,
INT3_dmaChannel1_m = 0x00000002,
INT3_dmaChannel2_b = 2,
INT3_dmaChannel2_m = 0x00000004,
INT3_dmaChannel3_b = 3,
INT3_dmaChannel3_m = 0x00000008,
INT3_dmaChannel4_b = 4,
INT3_dmaChannel4_m = 0x00000010,
INT3_dmaChannel5_b = 5,
INT3_dmaChannel5_m = 0x00000020,
INT5_uartGeneral0_b = 0,
INT5_uartGeneral0_m = 0x00000001,
INT5_uartTxrdy0_b = 1,
INT5_uartTxrdy0_m = 0x00000002,
INT5_uartRxrdy0_b = 2,
INT5_uartRxrdy0_m = 0x00000004,
INT5_pci_b = 3,
INT5_pci_m = 0x00000008,
INT5_pciDecoupled_b = 4,
INT5_pciDecoupled_m = 0x00000010,
INT5_spi_b = 5,
INT5_spi_m = 0x00000020,
INT5_deviceDecoupled_b = 6,
INT5_deviceDecoupled_m = 0x00000040,
INT5_eth0Ovr_b = 9,
INT5_eth0Ovr_m = 0x00000200,
INT5_eth0Und_b = 10,
INT5_eth0Und_m = 0x00000400,
INT5_eth0Pfd_b = 11,
INT5_eth0Pfd_m = 0x00000800,
INT5_nvram_b = 12,
INT5_nvram_m = 0x00001000,
INT6_gpio0_b = 0,
INT6_gpio0_m = 0x00000001,
INT6_gpio1_b = 1,
INT6_gpio1_m = 0x00000002,
INT6_gpio2_b = 2,
INT6_gpio2_m = 0x00000004,
INT6_gpio3_b = 3,
INT6_gpio3_m = 0x00000008,
INT6_gpio4_b = 4,
INT6_gpio4_m = 0x00000010,
INT6_gpio5_b = 5,
INT6_gpio5_m = 0x00000020,
INT6_gpio6_b = 6,
INT6_gpio6_m = 0x00000040,
INT6_gpio7_b = 7,
INT6_gpio7_m = 0x00000080,
INT6_gpio8_b = 8,
INT6_gpio8_m = 0x00000100,
INT6_gpio9_b = 9,
INT6_gpio9_m = 0x00000200,
INT6_gpio10_b = 10,
INT6_gpio10_m = 0x00000400,
INT6_gpio11_b = 11,
INT6_gpio11_m = 0x00000800,
INT6_gpio12_b = 12,
INT6_gpio12_m = 0x00001000,
INT6_gpio13_b = 13,
INT6_gpio13_m = 0x00002000,
NMIPS_gpio_b = 0,
NMIPS_gpio_m = 0x00000001,
} ;
#endif // __IDT_INT_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* System Integrity register definition
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_INTEG_H__
#define __IDT_INTEG_H__
enum
{
INTEG0_PhysicalAddress = 0x18030000,
INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
INTEG0_VirtualAddress = 0xB8030000,
INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
} ;
// if you are looking for CEA, try rst.h
typedef struct
{
u32 filler [0xc] ; // 0x30 bytes unused.
u32 errcs ; // sticky use ERRCS_
u32 wtcount ; // Watchdog timer count reg.
u32 wtcompare ; // Watchdog timer timeout value.
u32 wtc ; // Watchdog timer control. use WTC_
} volatile *INTEG_t ;
enum
{
ERRCS_wto_b = 0, // In INTEG_t -> errcs
ERRCS_wto_m = 0x00000001,
ERRCS_wne_b = 1, // In INTEG_t -> errcs
ERRCS_wne_m = 0x00000002,
ERRCS_ucw_b = 2, // In INTEG_t -> errcs
ERRCS_ucw_m = 0x00000004,
ERRCS_ucr_b = 3, // In INTEG_t -> errcs
ERRCS_ucr_m = 0x00000008,
ERRCS_upw_b = 4, // In INTEG_t -> errcs
ERRCS_upw_m = 0x00000010,
ERRCS_upr_b = 5, // In INTEG_t -> errcs
ERRCS_upr_m = 0x00000020,
ERRCS_udw_b = 6, // In INTEG_t -> errcs
ERRCS_udw_m = 0x00000040,
ERRCS_udr_b = 7, // In INTEG_t -> errcs
ERRCS_udr_m = 0x00000080,
ERRCS_sae_b = 8, // In INTEG_t -> errcs
ERRCS_sae_m = 0x00000100,
ERRCS_wre_b = 9, // In INTEG_t -> errcs
ERRCS_wre_m = 0x00000200,
WTC_en_b = 0, // In INTEG_t -> wtc
WTC_en_m = 0x00000001,
WTC_to_b = 1, // In INTEG_t -> wtc
WTC_to_m = 0x00000002,
} ;
#endif // __IDT_INTEG_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* IP Arbiter register definitions
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt,neb
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_IPARB_H__
#define __IDT_IPARB_H__
enum
{
IPARB0_PhysicalAddress = 0x18048000,
IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
IPARB0_VirtualAddress = 0xB8048000,
IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
} ;
enum
{
IPABMXC_ethernet0Receive = 0,
IPABMXC_ethernet0Transmit = 1,
IPABMXC_memoryToHoldFifo = 2,
IPABMXC_holdFifoToMemory = 3,
IPABMXC_pciToMemory = 4,
IPABMXC_memoryToPci = 5,
IPABMXC_pciTarget = 6,
IPABMXC_pciTargetStart = 7,
IPABMXC_cpuToIpBus = 8,
IPABMXC_Count, // Must be last in list !
IPABMXC_Min = IPABMXC_ethernet0Receive,
IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
} ;
typedef struct
{
u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
u32 ipac ; // use IPAC_
u32 ipaitcc; // use IPAITCC_
u32 ipaspare ;
} volatile * IPARB_t ;
enum
{
IPAC_dp_b = 0,
IPAC_dp_m = 0x00000001,
IPAC_dep_b = 1,
IPAC_dep_m = 0x00000002,
IPAC_drm_b = 2,
IPAC_drm_m = 0x00000004,
IPAC_dwm_b = 3,
IPAC_dwm_m = 0x00000008,
IPAC_msk_b = 4,
IPAC_msk_m = 0x00000010,
IPAPC_ptc_b = 0,
IPAPC_ptc_m = 0x00003fff,
IPAPC_mf_b = 14,
IPAPC_mf_m = 0x00004000,
IPAPC_cptc_b = 16,
IPAPC_cptc_m = 0x3fff0000,
IPAITCC_itcc = 0,
IPAITCC_itcc, = 0x000001ff,
IPABMC_mtc_b = 0,
IPABMC_mtc_m = 0x00000fff,
IPABMC_p_b = 12,
IPABMC_p_m = 0x00003000,
IPABMC_msk_b = 14,
IPABMC_msk_m = 0x00004000,
IPABMC_cmtc_b = 16,
IPABMC_cmtc_m = 0x0fff0000,
};
#endif // __IDT_IPARB_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* PCI register definitio
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_PCI_H__
#define __IDT_PCI_H__
enum
{
PCI0_PhysicalAddress = 0x18080000,
PCI_PhysicalAddress = PCI0_PhysicalAddress,
PCI0_VirtualAddress = 0xB8080000,
PCI_VirtualAddress = PCI0_VirtualAddress,
} ;
enum
{
PCI_LbaCount = 4, // Local base addresses.
} ;
typedef struct
{
u32 a ; // Address.
u32 c ; // Control.
u32 m ; // mapping.
} PCI_Map_s ;
typedef struct
{
u32 pcic ;
u32 pcis ;
u32 pcism ;
u32 pcicfga ;
u32 pcicfgd ;
PCI_Map_s pcilba [PCI_LbaCount] ;
u32 pcidac ;
u32 pcidas ;
u32 pcidasm ;
u32 pcidad ;
u32 pcidma8c ;
u32 pcidma9c ;
u32 pcitc ;
} volatile *PCI_t ;
// PCI messaging unit.
enum
{
PCIM_Count = 2,
} ;
typedef struct
{
u32 pciim [PCIM_Count] ;
u32 pciom [PCIM_Count] ;
u32 pciid ;
u32 pciiic ;
u32 pciiim ;
u32 pciiod ;
u32 pciioic ;
u32 pciioim ;
} volatile *PCIM_t ;
/*******************************************************************************
*
* PCI Control Register
*
******************************************************************************/
enum
{
PCIC_en_b = 0,
PCIC_en_m = 0x00000001,
PCIC_tnr_b = 1,
PCIC_tnr_m = 0x00000002,
PCIC_sce_b = 2,
PCIC_sce_m = 0x00000004,
PCIC_ien_b = 3,
PCIC_ien_m = 0x00000008,
PCIC_aaa_b = 4,
PCIC_aaa_m = 0x00000010,
PCIC_eap_b = 5,
PCIC_eap_m = 0x00000020,
PCIC_pcim_b = 6,
PCIC_pcim_m = 0x000001c0,
PCIC_pcim_disabled_v = 0,
PCIC_pcim_tnr_v = 1, // Satellite - target not ready
PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
PCIC_pcim_extern_v = 3, // Host - external arbiter.
PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
PCIC_pcim_reserved6_v = 6,
PCIC_pcim_reserved7_v = 7,
PCIC_igm_b = 9,
PCIC_igm_m = 0x00000200,
} ;
/*******************************************************************************
*
* PCI Status Register
*
******************************************************************************/
enum {
PCIS_eed_b = 0,
PCIS_eed_m = 0x00000001,
PCIS_wr_b = 1,
PCIS_wr_m = 0x00000002,
PCIS_nmi_b = 2,
PCIS_nmi_m = 0x00000004,
PCIS_ii_b = 3,
PCIS_ii_m = 0x00000008,
PCIS_cwe_b = 4,
PCIS_cwe_m = 0x00000010,
PCIS_cre_b = 5,
PCIS_cre_m = 0x00000020,
PCIS_mdpe_b = 6,
PCIS_mdpe_m = 0x00000040,
PCIS_sta_b = 7,
PCIS_sta_m = 0x00000080,
PCIS_rta_b = 8,
PCIS_rta_m = 0x00000100,
PCIS_rma_b = 9,
PCIS_rma_m = 0x00000200,
PCIS_sse_b = 10,
PCIS_sse_m = 0x00000400,
PCIS_ose_b = 11,
PCIS_ose_m = 0x00000800,
PCIS_pe_b = 12,
PCIS_pe_m = 0x00001000,
PCIS_tae_b = 13,
PCIS_tae_m = 0x00002000,
PCIS_rle_b = 14,
PCIS_rle_m = 0x00004000,
PCIS_bme_b = 15,
PCIS_bme_m = 0x00008000,
PCIS_prd_b = 16,
PCIS_prd_m = 0x00010000,
PCIS_rip_b = 17,
PCIS_rip_m = 0x00020000,
} ;
/*******************************************************************************
*
* PCI Status Mask Register
*
******************************************************************************/
enum {
PCISM_eed_b = 0,
PCISM_eed_m = 0x00000001,
PCISM_wr_b = 1,
PCISM_wr_m = 0x00000002,
PCISM_nmi_b = 2,
PCISM_nmi_m = 0x00000004,
PCISM_ii_b = 3,
PCISM_ii_m = 0x00000008,
PCISM_cwe_b = 4,
PCISM_cwe_m = 0x00000010,
PCISM_cre_b = 5,
PCISM_cre_m = 0x00000020,
PCISM_mdpe_b = 6,
PCISM_mdpe_m = 0x00000040,
PCISM_sta_b = 7,
PCISM_sta_m = 0x00000080,
PCISM_rta_b = 8,
PCISM_rta_m = 0x00000100,
PCISM_rma_b = 9,
PCISM_rma_m = 0x00000200,
PCISM_sse_b = 10,
PCISM_sse_m = 0x00000400,
PCISM_ose_b = 11,
PCISM_ose_m = 0x00000800,
PCISM_pe_b = 12,
PCISM_pe_m = 0x00001000,
PCISM_tae_b = 13,
PCISM_tae_m = 0x00002000,
PCISM_rle_b = 14,
PCISM_rle_m = 0x00004000,
PCISM_bme_b = 15,
PCISM_bme_m = 0x00008000,
PCISM_prd_b = 16,
PCISM_prd_m = 0x00010000,
PCISM_rip_b = 17,
PCISM_rip_m = 0x00020000,
} ;
/*******************************************************************************
*
* PCI Configuration Address Register
*
******************************************************************************/
enum {
PCICFGA_reg_b = 2,
PCICFGA_reg_m = 0x000000fc,
PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
PCICFGA_reg_pba0m_v = 0x48>>2,
PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
PCICFGA_reg_pba1m_v = 0x50>>2,
PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
PCICFGA_reg_pba2m_v = 0x58>>2,
PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
PCICFGA_reg_pba3m_v = 0x60>>2,
PCICFGA_reg_pmgt_v = 0x64>>2,
PCICFGA_func_b = 8,
PCICFGA_func_m = 0x00000700,
PCICFGA_dev_b = 11,
PCICFGA_dev_m = 0x0000f800,
PCICFGA_dev_internal_v = 0,
PCICFGA_bus_b = 16,
PCICFGA_bus_m = 0x00ff0000,
PCICFGA_bus_type0_v = 0, //local bus
PCICFGA_en_b = 31, // read only
PCICFGA_en_m = 0x80000000,
} ;
enum {
PCFGID_vendor_b = 0,
PCFGID_vendor_m = 0x0000ffff,
PCFGID_vendor_IDT_v = 0x111d,
PCFGID_device_b = 16,
PCFGID_device_m = 0xffff0000,
PCFGID_device_Korinade_v = 0x0214,
PCFG04_command_ioena_b = 1,
PCFG04_command_ioena_m = 0x00000001,
PCFG04_command_memena_b = 2,
PCFG04_command_memena_m = 0x00000002,
PCFG04_command_bmena_b = 3,
PCFG04_command_bmena_m = 0x00000004,
PCFG04_command_mwinv_b = 5,
PCFG04_command_mwinv_m = 0x00000010,
PCFG04_command_parena_b = 7,
PCFG04_command_parena_m = 0x00000040,
PCFG04_command_serrena_b = 9,
PCFG04_command_serrena_m = 0x00000100,
PCFG04_command_fastbbena_b = 10,
PCFG04_command_fastbbena_m = 0x00000200,
PCFG04_status_b = 16,
PCFG04_status_m = 0xffff0000,
PCFG04_status_66MHz_b = 21, // 66 MHz enable
PCFG04_status_66MHz_m = 0x00200000,
PCFG04_status_fbb_b = 23,
PCFG04_status_fbb_m = 0x00800000,
PCFG04_status_mdpe_b = 24,
PCFG04_status_mdpe_m = 0x01000000,
PCFG04_status_dst_b = 25,
PCFG04_status_dst_m = 0x06000000,
PCFG04_status_sta_b = 27,
PCFG04_status_sta_m = 0x08000000,
PCFG04_status_rta_b = 28,
PCFG04_status_rta_m = 0x10000000,
PCFG04_status_rma_b = 29,
PCFG04_status_rma_m = 0x20000000,
PCFG04_status_sse_b = 30,
PCFG04_status_sse_m = 0x40000000,
PCFG04_status_pe_b = 31,
PCFG04_status_pe_m = 0x40000000,
PCFG08_revId_b = 0,
PCFG08_revId_m = 0x000000ff,
PCFG08_classCode_b = 0,
PCFG08_classCode_m = 0xffffff00,
PCFG08_classCode_bridge_v = 06,
PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
PCFG0C_cacheline_b = 0,
PCFG0C_cacheline_m = 0x000000ff,
PCFG0C_masterLatency_b = 8,
PCFG0C_masterLatency_m = 0x0000ff00,
PCFG0C_headerType_b = 16,
PCFG0C_headerType_m = 0x00ff0000,
PCFG0C_bist_b = 24,
PCFG0C_bist_m = 0xff000000,
PCIPBA_msi_b = 0,
PCIPBA_msi_m = 0x00000001,
PCIPBA_p_b = 3,
PCIPBA_p_m = 0x00000004,
PCIPBA_baddr_b = 8,
PCIPBA_baddr_m = 0xffffff00,
PCFGSS_vendorId_b = 0,
PCFGSS_vendorId_m = 0x0000ffff,
PCFGSS_id_b = 16,
PCFGSS_id_m = 0xffff0000,
PCFG3C_interruptLine_b = 0,
PCFG3C_interruptLine_m = 0x000000ff,
PCFG3C_interruptPin_b = 8,
PCFG3C_interruptPin_m = 0x0000ff00,
PCFG3C_minGrant_b = 16,
PCFG3C_minGrant_m = 0x00ff0000,
PCFG3C_maxLat_b = 24,
PCFG3C_maxLat_m = 0xff000000,
PCIPBAC_msi_b = 0,
PCIPBAC_msi_m = 0x00000001,
PCIPBAC_p_b = 1,
PCIPBAC_p_m = 0x00000002,
PCIPBAC_size_b = 2,
PCIPBAC_size_m = 0x0000007c,
PCIPBAC_sb_b = 7,
PCIPBAC_sb_m = 0x00000080,
PCIPBAC_pp_b = 8,
PCIPBAC_pp_m = 0x00000100,
PCIPBAC_mr_b = 9,
PCIPBAC_mr_m = 0x00000600,
PCIPBAC_mr_read_v =0, //no prefetching
PCIPBAC_mr_readLine_v =1,
PCIPBAC_mr_readMult_v =2,
PCIPBAC_mrl_b = 11,
PCIPBAC_mrl_m = 0x00000800,
PCIPBAC_mrm_b = 12,
PCIPBAC_mrm_m = 0x00001000,
PCIPBAC_trp_b = 13,
PCIPBAC_trp_m = 0x00002000,
PCFG40_trdyTimeout_b = 0,
PCFG40_trdyTimeout_m = 0x000000ff,
PCFG40_retryLim_b = 8,
PCFG40_retryLim_m = 0x0000ff00,
};
/*******************************************************************************
*
* PCI Local Base Address [0|1|2|3] Register
*
******************************************************************************/
enum {
PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
PCILBA_baddr_m = 0xffffff00,
} ;
/*******************************************************************************
*
* PCI Local Base Address Control Register
*
******************************************************************************/
enum {
PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
PCILBAC_msi_m = 0x00000001,
PCILBAC_msi_mem_v = 0,
PCILBAC_msi_io_v = 1,
PCILBAC_size_b = 2, // In pPci->pcilba[i].c
PCILBAC_size_m = 0x0000007c,
PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
PCILBAC_sb_m = 0x00000080,
PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
PCILBAC_rt_m = 0x00000100,
PCILBAC_rt_noprefetch_v = 0, // mem read
PCILBAC_rt_prefetch_v = 1, // mem readline
} ;
/*******************************************************************************
*
* PCI Local Base Address [0|1|2|3] Mapping Register
*
******************************************************************************/
enum {
PCILBAM_maddr_b = 8,
PCILBAM_maddr_m = 0xffffff00,
} ;
/*******************************************************************************
*
* PCI Decoupled Access Control Register
*
******************************************************************************/
enum {
PCIDAC_den_b = 0,
PCIDAC_den_m = 0x00000001,
} ;
/*******************************************************************************
*
* PCI Decoupled Access Status Register
*
******************************************************************************/
enum {
PCIDAS_d_b = 0,
PCIDAS_d_m = 0x00000001,
PCIDAS_b_b = 1,
PCIDAS_b_m = 0x00000002,
PCIDAS_e_b = 2,
PCIDAS_e_m = 0x00000004,
PCIDAS_ofe_b = 3,
PCIDAS_ofe_m = 0x00000008,
PCIDAS_off_b = 4,
PCIDAS_off_m = 0x00000010,
PCIDAS_ife_b = 5,
PCIDAS_ife_m = 0x00000020,
PCIDAS_iff_b = 6,
PCIDAS_iff_m = 0x00000040,
} ;
/*******************************************************************************
*
* PCI DMA Channel 8 Configuration Register
*
******************************************************************************/
enum
{
PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
} ;
/*******************************************************************************
*
* PCI DMA Channel 9 Configuration Register
*
******************************************************************************/
enum
{
PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
} ;
/*******************************************************************************
*
* PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
*
******************************************************************************/
enum {
PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
// These are for reads (DMA channel 8)
PCIDMAD_devcmd_mr_v = 0, //memory read
PCIDMAD_devcmd_mrl_v = 1, //memory read line
PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
PCIDMAD_devcmd_ior_v = 3, //I/O read
// These are for writes (DMA channel 9)
PCIDMAD_devcmd_mw_v = 0, //memory write
PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
PCIDMAD_devcmd_iow_v = 3, //I/O write
// Swap byte field applies to both DMA channel 8 and 9
PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
PCIDMAD_sb_m = 0x01000000, // swap byte field
} ;
/*******************************************************************************
*
* PCI Target Control Register
*
******************************************************************************/
enum
{
PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
PCITC_rtimer_m = 0x000000ff,
PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
PCITC_dtimer_m = 0x0000ff00,
PCITC_rdr_b = 18, // In PCITC_t -> pcitc
PCITC_rdr_m = 0x00040000,
PCITC_ddt_b = 19, // In PCITC_t -> pcitc
PCITC_ddt_m = 0x00080000,
} ;
/*******************************************************************************
*
* PCI messaging unit [applies to both inbound and outbound registers ]
*
******************************************************************************/
enum
{
PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
PCIM_m0_m = 0x00000001, // inbound or outbound message 0
PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
PCIM_m1_m = 0x00000002, // inbound or outbound message 1
PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
PCIM_db_m = 0x00000004, // inbound or outbound doorbell
};
#define PCI_MSG_VirtualAddress 0xB8088010
#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
#define PCIM_SHFT 0x6
#define PCIM_BIT_LEN 0x7
#define PCIM_H_EA 0x3
#define PCIM_H_IA_FIX 0x4
#define PCIM_H_IA_RR 0x5
#if 0
#define PCI_ADDR_START 0x13000000
#endif
#define PCI_ADDR_START 0x50000000
#define CPUTOPCI_MEM_WIN 0x02000000
#define CPUTOPCI_IO_WIN 0x00100000
#define PCILBA_SIZE_SHFT 2
#define PCILBA_SIZE_MASK 0x1F
#define SIZE_256MB 0x1C
#define SIZE_128MB 0x1B
#define SIZE_64MB 0x1A
#define SIZE_32MB 0x19
#define SIZE_16MB 0x18
#define SIZE_4MB 0x16
#define SIZE_2MB 0x15
#define SIZE_1MB 0x14
#define KORINA_CONFIG0_ADDR 0x80000000
#define KORINA_CONFIG1_ADDR 0x80000004
#define KORINA_CONFIG2_ADDR 0x80000008
#define KORINA_CONFIG3_ADDR 0x8000000C
#define KORINA_CONFIG4_ADDR 0x80000010
#define KORINA_CONFIG5_ADDR 0x80000014
#define KORINA_CONFIG6_ADDR 0x80000018
#define KORINA_CONFIG7_ADDR 0x8000001C
#define KORINA_CONFIG8_ADDR 0x80000020
#define KORINA_CONFIG9_ADDR 0x80000024
#define KORINA_CONFIG10_ADDR 0x80000028
#define KORINA_CONFIG11_ADDR 0x8000002C
#define KORINA_CONFIG12_ADDR 0x80000030
#define KORINA_CONFIG13_ADDR 0x80000034
#define KORINA_CONFIG14_ADDR 0x80000038
#define KORINA_CONFIG15_ADDR 0x8000003C
#define KORINA_CONFIG16_ADDR 0x80000040
#define KORINA_CONFIG17_ADDR 0x80000044
#define KORINA_CONFIG18_ADDR 0x80000048
#define KORINA_CONFIG19_ADDR 0x8000004C
#define KORINA_CONFIG20_ADDR 0x80000050
#define KORINA_CONFIG21_ADDR 0x80000054
#define KORINA_CONFIG22_ADDR 0x80000058
#define KORINA_CONFIG23_ADDR 0x8000005C
#define KORINA_CONFIG24_ADDR 0x80000060
#define KORINA_CONFIG25_ADDR 0x80000064
#define KORINA_CMD (PCFG04_command_ioena_m | \
PCFG04_command_memena_m | \
PCFG04_command_bmena_m | \
PCFG04_command_mwinv_m | \
PCFG04_command_parena_m | \
PCFG04_command_serrena_m )
#define KORINA_STAT (PCFG04_status_mdpe_m | \
PCFG04_status_sta_m | \
PCFG04_status_rta_m | \
PCFG04_status_rma_m | \
PCFG04_status_sse_m | \
PCFG04_status_pe_m)
#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
#define KORINA_REVID 0
#define KORINA_CLASS_CODE 0
#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
KORINA_REVID)
#define KORINA_CACHE_LINE_SIZE 4
#define KORINA_MASTER_LAT 0x3c
#define KORINA_HEADER_TYPE 0
#define KORINA_BIST 0
#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
(KORINA_HEADER_TYPE<<16) | \
(KORINA_MASTER_LAT<<8) | \
KORINA_CACHE_LINE_SIZE )
#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
#define KORINA_BAR1 0x18800001 /* 1 MB IO */
#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
internal Registers */
#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
#define KORINA_CNFG4 KORINA_BAR0
#define KORINA_CNFG5 KORINA_BAR1
#define KORINA_CNFG6 KORINA_BAR2
#define KORINA_CNFG7 KORINA_BAR3
#define KORINA_SUBSYS_VENDOR_ID 0x011d
#define KORINA_SUBSYSTEM_ID 0x0214
#define KORINA_CNFG8 0
#define KORINA_CNFG9 0
#define KORINA_CNFG10 0
#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
KORINA_SUBSYSTEM_ID)
#define KORINA_INT_LINE 1
#define KORINA_INT_PIN 1
#define KORINA_MIN_GNT 8
#define KORINA_MAX_LAT 0x38
#define KORINA_CNFG12 0
#define KORINA_CNFG13 0
#define KORINA_CNFG14 0
#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
(KORINA_MIN_GNT<<16) | \
(KORINA_INT_PIN<<8) | \
KORINA_INT_LINE)
#define KORINA_RETRY_LIMIT 0x80
#define KORINA_TRDY_LIMIT 0x80
#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
KORINA_TRDY_LIMIT)
#define PCI_PBAxC_R 0x0
#define PCI_PBAxC_RL 0x1
#define PCI_PBAxC_RM 0x2
#define SIZE_SHFT 2
#if defined(__MIPSEB__)
#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
PCIPBAC_pp_m | \
(SIZE_128MB<<SIZE_SHFT) | \
PCIPBAC_p_m)
#else
#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
PCIPBAC_pp_m | \
(SIZE_128MB<<SIZE_SHFT) | \
PCIPBAC_p_m)
#endif
#define KORINA_CNFG17 KORINA_PBA0C
#define KORINA_PBA0M 0x0
#define KORINA_CNFG18 KORINA_PBA0M
#if defined(__MIPSEB__)
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
PCIPBAC_msi_m)
#else
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
PCIPBAC_msi_m)
#endif
#define KORINA_CNFG19 KORINA_PBA1C
#define KORINA_PBA1M 0x0
#define KORINA_CNFG20 KORINA_PBA1M
#if defined(__MIPSEB__)
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
PCIPBAC_msi_m)
#else
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
PCIPBAC_msi_m)
#endif
#define KORINA_CNFG21 KORINA_PBA2C
#define KORINA_PBA2M 0x18000000
#define KORINA_CNFG22 KORINA_PBA2M
#define KORINA_PBA3C 0
#define KORINA_CNFG23 KORINA_PBA3C
#define KORINA_PBA3M 0
#define KORINA_CNFG24 KORINA_PBA3M
#define PCITC_DTIMER_VAL 8
#define PCITC_RTIMER_VAL 0x10
#endif // __IDT_PCI_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Reset register definitions.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_RST_H__
#define __IDT_RST_H__
enum
{
RST0_PhysicalAddress = 0x18000000,
RST_PhysicalAddress = RST0_PhysicalAddress, // Default
RST0_VirtualAddress = 0xb8000000,
RST_VirtualAddress = RST0_VirtualAddress, // Default
} ;
typedef struct RST_s
{
u32 filler [0x0006] ;
u32 sysid ;
u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
u32 reset ;
u32 bcv ;
u32 cea ;
} volatile * RST_t ;
enum
{
SYSID_rev_b = 0,
SYSID_rev_m = 0x000000ff,
SYSID_imp_b = 8,
SYSID_imp_m = 0x000fff00,
SYSID_vendor_b = 8,
SYSID_vendor_m = 0xfff00000,
BCV_pll_b = 0,
BCV_pll_m = 0x0000000f,
BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
BCV_pll_Res9_v = 0x9,
BCV_pll_Res10_v = 0xa,
BCV_pll_Res11_v = 0xb,
BCV_pll_Res12_v = 0xc,
BCV_pll_Res13_v = 0xd,
BCV_pll_Res14_v = 0xe,
BCV_pll_Res15_v = 0xf,
BCV_clkDiv_b = 4,
BCV_clkDiv_m = 0x00000030,
BCV_clkDiv_Div1_v = 0x0,
BCV_clkDiv_Div2_v = 0x1,
BCV_clkDiv_Div4_v = 0x2,
BCV_clkDiv_Res3_v = 0x3,
BCV_bigEndian_b = 6,
BCV_bigEndian_m = 0x00000040,
BCV_resetFast_b = 7,
BCV_resetFast_m = 0x00000080,
BCV_pciMode_b = 8,
BCV_pciMode_m = 0x00000700,
BCV_pciMode_disabled_v = 0, // PCI is disabled.
BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
BCV_pciMode_external_v = 3, // host, external arbiter.
BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
BCV_pciMode_res6_v = 6,
BCV_pciMode_res7_v = 7,
BCV_watchDisable_b = 11,
BCV_watchDisable_m = 0x00000800,
BCV_res12_b = 12,
BCV_res12_m = 0x00001000,
BCV_res13_b = 13,
BCV_res13_m = 0x00002000,
BCV_res14_b = 14,
BCV_res14_m = 0x00004000,
BCV_res15_b = 15,
BCV_res15_m = 0x00008000,
} ;
#endif // __IDT_RST_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Serial Peripheral Interface register definitions.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_SPI_H__
#define __IDT_SPI_H__
enum
{
SPI0_PhysicalAddress = 0x18070000,
SPI_PhysicalAddress = SPI0_PhysicalAddress,
SPI0_VirtualAddress = 0xB8070000,
SPI_VirtualAddress = SPI0_VirtualAddress,
} ;
typedef struct
{
u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
u32 spc ; // spi control reg use SPC_
u32 sps ; // spi status reg use SPS_
u32 spd ; // spi data reg use SPD_
u32 siofunc ; // serial IO function use SIOFUNC_
u32 siocfg ; // serial IO config use SIOCFG_
u32 siod; // serial IO data use SIOD_
} volatile *SPI_t ;
enum
{
SPCP_div_b = 0,
SPCP_div_m = 0x000000ff,
SPC_spr_b = 0,
SPC_spr_m = 0x00000003,
SPC_spr_div2_v = 0,
SPC_spr_div4_v = 1,
SPC_spr_div16_v = 2,
SPC_spr_div32_v = 3,
SPC_cpha_b = 2,
SPC_cpha_m = 0x00000004,
SPC_cpol_b = 3,
SPC_cpol_m = 0x00000008,
SPC_mstr_b = 4,
SPC_mstr_m = 0x00000010,
SPC_spe_b = 6,
SPC_spe_m = 0x00000040,
SPC_spie_b = 7,
SPC_spie_m = 0x00000080,
SPS_modf_b = 4,
SPS_modf_m = 0x00000010,
SPS_wcol_b = 6,
SPS_wcol_m = 0x00000040,
SPS_spif_b = 7,
SPS_spif_m = 0x00000070,
SPD_data_b = 0,
SPD_data_m = 0x000000ff,
SIOFUNC_sdo_b = 0,
SIOFUNC_sdo_m = 0x00000001,
SIOFUNC_sdi_b = 1,
SIOFUNC_sdi_m = 0x00000002,
SIOFUNC_sck_b = 2,
SIOFUNC_sck_m = 0x00000004,
SIOFUNC_pci_b = 3,
SIOFUNC_pci_m = 0x00000008,
SIOCFG_sdo_b = 0,
SIOCFG_sdo_m = 0x00000001,
SIOCFG_sdi_b = 1,
SIOCFG_sdi_m = 0x00000002,
SIOCFG_sck_b = 2,
SIOCFG_sck_m = 0x00000004,
SIOCFG_pci_b = 3,
SIOCFG_pci_m = 0x00000008,
SIOD_sdo_b = 0,
SIOD_sdo_m = 0x00000001,
SIOD_sdi_b = 1,
SIOD_sdi_m = 0x00000002,
SIOD_sck_b = 2,
SIOD_sck_m = 0x00000004,
SIOD_pci_b = 3,
SIOD_pci_m = 0x00000008,
} ;
#endif // __IDT_SPI_H__

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/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* Definitions for timer registers
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt,neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_TIM_H__
#define __IDT_TIM_H__
enum
{
TIM0_PhysicalAddress = 0x18028000,
TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
TIM0_VirtualAddress = 0xb8028000,
TIM_VirtualAddress = TIM0_VirtualAddress, // Default
} ;
enum
{
TIM_Count = 3,
} ;
struct TIM_CNTR_s
{
u32 count ;
u32 compare ;
u32 ctc ; //use CTC_
} ;
typedef struct TIM_s
{
struct TIM_CNTR_s tim [TIM_Count] ;
u32 rcount ; //use RCOUNT_
u32 rcompare ; //use RCOMPARE_
u32 rtc ; //use RTC_
} volatile * TIM_t ;
enum
{
CTC_en_b = 0,
CTC_en_m = 0x00000001,
CTC_to_b = 1,
CTC_to_m = 0x00000002,
RCOUNT_count_b = 0,
RCOUNT_count_m = 0x0000ffff,
RCOMPARE_compare_b = 0,
RCOMPARE_compare_m = 0x0000ffff,
RTC_ce_b = 0,
RTC_ce_m = 0x00000001,
RTC_to_b = 1,
RTC_to_m = 0x00000002,
RTC_rqe_b = 2,
RTC_rqe_m = 0x00000004,
} ;
#endif // __IDT_TIM_H__

189
target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_uart.h Normal file
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@ -0,0 +1,189 @@
/**************************************************************************
*
* BRIEF MODULE DESCRIPTION
* UART register definitions
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
**************************************************************************
* May 2004 rkt, neb.
*
* Initial Release
*
*
*
**************************************************************************
*/
#ifndef __IDT_UART_H__
#define __IDT_UART_H__
enum
{
UART0_PhysicalAddress = 0x1c000000,
UART_PhysicalAddress = UART0_PhysicalAddress, // Default
UART0_VirtualAddress = 0xbc000000,
UART_VirtualAddress = UART0_VirtualAddress, // Default
} ;
/*
* Register definitions are in bytes so we can handle endian problems.
*/
typedef struct UART_s
{
union
{
u32 const uartrb ; // 0x00 - DLAB=0, read.
u32 uartth ; // 0x00 - DLAB=0, write.
u32 uartdll ; // 0x00 - DLAB=1, read/write.
} ;
union
{
u32 uartie ; // 0x04 - DLAB=0, read/write.
u32 uartdlh ; // 0x04 - DLAB=1, read/write.
} ;
union
{
u32 const uartii ; // 0x08 - DLAB=0, read.
u32 uartfc ; // 0x08 - DLAB=0, write.
} ;
u32 uartlc ; // 0x0c
u32 uartmc ; // 0x10
u32 uartls ; // 0x14
u32 uartms ; // 0x18
u32 uarts ; // 0x1c
} volatile *UART_t ;
// Reset registers.
typedef u32 volatile *UARTRR_t ;
enum
{
UARTIE_rda_b = 0,
UARTIE_rda_m = 0x00000001,
UARTIE_the_b = 1,
UARTIE_the_m = 0x00000002,
UARTIE_rls_b = 2,
UARTIE_rls_m = 0x00000004,
UARTIE_ems_b = 3,
UARTIE_ems_m = 0x00000008,
UARTII_pi_b = 0,
UARTII_pi_m = 0x00000001,
UARTII_iid_b = 1,
UARTII_iid_m = 0x0000000e,
UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
UARTII_iid_rda_v = 2, // Receive data available
UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
UARTII_iid_res4_v = 4, // reserved.
UARTII_iid_res5_v = 5, // reserved.
UARTII_iid_cto_v = 6, // Character timeout.
UARTII_iid_res7_v = 7, // reserved.
UARTFC_en_b = 0,
UARTFC_en_m = 0x00000001,
UARTFC_rr_b = 1,
UARTFC_rr_m = 0x00000002,
UARTFC_tr_b = 2,
UARTFC_tr_m = 0x00000004,
UARTFC_dms_b = 3,
UARTFC_dms_m = 0x00000008,
UARTFC_rt_b = 6,
UARTFC_rt_m = 0x000000c0,
UARTFC_rt_1Byte_v = 0,
UARTFC_rt_4Byte_v = 1,
UARTFC_rt_8Byte_v = 2,
UARTFC_rt_14Byte_v = 3,
UARTLC_wls_b = 0,
UARTLC_wls_m = 0x00000003,
UARTLC_wls_5Bits_v = 0,
UARTLC_wls_6Bits_v = 1,
UARTLC_wls_7Bits_v = 2,
UARTLC_wls_8Bits_v = 3,
UARTLC_stb_b = 2,
UARTLC_stb_m = 0x00000004,
UARTLC_pen_b = 3,
UARTLC_pen_m = 0x00000008,
UARTLC_eps_b = 4,
UARTLC_eps_m = 0x00000010,
UARTLC_sp_b = 5,
UARTLC_sp_m = 0x00000020,
UARTLC_sb_b = 6,
UARTLC_sb_m = 0x00000040,
UARTLC_dlab_b = 7,
UARTLC_dlab_m = 0x00000080,
UARTMC_dtr_b = 0,
UARTMC_dtr_m = 0x00000001,
UARTMC_rts_b = 1,
UARTMC_rts_m = 0x00000002,
UARTMC_o1_b = 2,
UARTMC_o1_m = 0x00000004,
UARTMC_o2_b = 3,
UARTMC_o2_m = 0x00000008,
UARTMC_lp_b = 4,
UARTMC_lp_m = 0x00000010,
UARTLS_dr_b = 0,
UARTLS_dr_m = 0x00000001,
UARTLS_oe_b = 1,
UARTLS_oe_m = 0x00000002,
UARTLS_pe_b = 2,
UARTLS_pe_m = 0x00000004,
UARTLS_fe_b = 3,
UARTLS_fe_m = 0x00000008,
UARTLS_bi_b = 4,
UARTLS_bi_m = 0x00000010,
UARTLS_thr_b = 5,
UARTLS_thr_m = 0x00000020,
UARTLS_te_b = 6,
UARTLS_te_m = 0x00000040,
UARTLS_rfe_b = 7,
UARTLS_rfe_m = 0x00000080,
UARTMS_dcts_b = 0,
UARTMS_dcts_m = 0x00000001,
UARTMS_ddsr_b = 1,
UARTMS_ddsr_m = 0x00000002,
UARTMS_teri_b = 2,
UARTMS_teri_m = 0x00000004,
UARTMS_ddcd_b = 3,
UARTMS_ddcd_m = 0x00000008,
UARTMS_cts_b = 4,
UARTMS_cts_m = 0x00000010,
UARTMS_dsr_b = 5,
UARTMS_dsr_m = 0x00000020,
UARTMS_ri_b = 6,
UARTMS_ri_m = 0x00000040,
UARTMS_dcd_b = 7,
UARTMS_dcd_m = 0x00000080,
} ;
#endif // __IDT_UART_H__

10285
target/linux/aruba-2.6/patches/000-aruba.patch
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File diff suppressed because it is too large Load diff

31
target/linux/aruba-2.6/patches/001-flash.patch
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@ -1,34 +1,3 @@
diff -Nur linux-2.6.15/arch/mips/aruba/flash_lock.c linux-2.6.15-openwrt/arch/mips/aruba/flash_lock.c
--- linux-2.6.15/arch/mips/aruba/flash_lock.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/aruba/flash_lock.c 2006-01-10 00:32:32.000000000 +0100
@@ -0,0 +1,27 @@
+#include <linux/module.h>
+#include <linux/types.h>
+#include <asm/bootinfo.h>
+
+#define AP70_PROT_ADDR 0xb8010008
+#define AP70_PROT_DATA 0x8
+#define AP60_PROT_ADDR 0xB8400000
+#define AP60_PROT_DATA 0x04000000
+
+void unlock_ap60_70_flash(void)
+{
+ volatile __u32 val;
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ val = *(volatile __u32 *)AP70_PROT_ADDR;
+ val &= ~(AP70_PROT_DATA);
+ *(volatile __u32 *)AP70_PROT_ADDR = val;
+ break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ val = *(volatile __u32 *)AP60_PROT_ADDR;
+ val &= ~(AP60_PROT_DATA);
+ *(volatile __u32 *)AP60_PROT_ADDR = val;
+ break;
+ }
+}
diff -Nur linux-2.6.15/drivers/mtd/chips/cfi_probe.c linux-2.6.15-openwrt/drivers/mtd/chips/cfi_probe.c
--- linux-2.6.15/drivers/mtd/chips/cfi_probe.c 2006-01-03 04:21:10.000000000 +0100
+++ linux-2.6.15-openwrt/drivers/mtd/chips/cfi_probe.c 2006-01-10 00:32:32.000000000 +0100

289
target/linux/aruba-2.6/patches/002-irq.patch
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@ -1,289 +0,0 @@
diff -Nur linux-2.6.17/arch/mips/aruba/irq.c linux-2.6.17-openwrt/arch/mips/aruba/irq.c
--- linux-2.6.17/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.17-openwrt/arch/mips/aruba/irq.c 2006-10-12 14:32:40.026285000 -0700
@@ -0,0 +1,285 @@
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_gpio.h>
+
+#include <asm/irq.h>
+
+extern void aruba_timer_interrupt(struct pt_regs *regs);
+
+typedef struct {
+ u32 mask;
+ volatile u32 *base_addr;
+} intr_group_t;
+
+static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
+ {0x00000000, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
+};
+
+#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
+#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003014)))
+#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)(0xbc003014))) = (val), READ_MASK_MERLOT())
+
+static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
+ {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
+ {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
+ {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
+ {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
+};
+
+#define READ_PEND_MUSCAT(base) (*(base))
+#define READ_MASK_MUSCAT(base) (*(base + 2))
+#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
+
+static inline int group_to_ip(unsigned int group)
+{
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ return group + 2;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ return 6;
+ }
+}
+
+static inline void enable_local_irq(unsigned int irq)
+{
+ clear_c0_cause(0x100 << irq);
+ set_c0_status(0x100 << irq);
+ irq_enable_hazard();
+}
+
+static inline void disable_local_irq(unsigned int irq)
+{
+ clear_c0_status(0x100 << irq);
+ clear_c0_cause(0x100 << irq);
+ irq_disable_hazard();
+}
+
+static inline void aruba_irq_enable(unsigned int irq)
+{
+ unsigned long flags;
+ unsigned int group, intr_bit;
+ volatile unsigned int *addr;
+
+ local_irq_save(flags);
+
+ if (irq < GROUP0_IRQ_BASE) {
+ enable_local_irq(irq);
+ } else {
+ int ip = irq - GROUP0_IRQ_BASE;
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ if (irq >= GROUP4_IRQ_BASE)
+ idt_gpio->gpioistat &= ~(1 << (irq - GROUP4_IRQ_BASE));
+
+ // irqs are in groups of 32
+ // ip is set to the remainder
+ group = ip >> 5;
+ ip &= 0x1f;
+
+ // bit -> 0 = unmask
+ intr_bit = 1 << ip;
+ addr = intr_group_muscat[group].base_addr;
+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
+ break;
+
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ group = 0;
+
+ // bit -> 1 = unmasked
+ intr_bit = 1 << ip;
+ addr = intr_group_merlot[group].base_addr;
+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
+ break;
+ }
+ enable_local_irq(group_to_ip(group));
+ }
+
+ back_to_back_c0_hazard();
+ local_irq_restore(flags);
+}
+
+static void aruba_irq_disable(unsigned int irq)
+{
+ unsigned long flags;
+ unsigned int group, intr_bit, mask;
+ volatile unsigned int *addr;
+
+ local_irq_save(flags);
+
+ if (irq < GROUP0_IRQ_BASE) {
+ disable_local_irq(irq);
+ } else {
+ int ip = irq - GROUP0_IRQ_BASE;
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ idt_gpio->gpioistat &= ~(1 << ip);
+
+ // irqs are in groups of 32
+ // ip is set to the remainder
+ group = ip >> 5;
+ ip &= 0x1f;
+
+ // bit -> 1 = mask
+ intr_bit = 1 << ip;
+ addr = intr_group_muscat[group].base_addr;
+
+ mask = READ_MASK_MUSCAT(addr);
+ mask |= intr_bit;
+ WRITE_MASK_MUSCAT(addr, mask);
+
+ if (mask == intr_group_muscat[group].mask) {
+ disable_local_irq(group_to_ip(group));
+ }
+ break;
+
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ group = 0;
+
+ // bit -> 0 = masked
+ intr_bit = 1 << ip;
+ addr = intr_group_merlot[group].base_addr;
+
+ mask = READ_MASK_MERLOT(addr);
+ mask &= ~intr_bit;
+ WRITE_MASK_MERLOT(addr, mask);
+
+ if (mask == intr_group_merlot[group].mask) {
+ disable_local_irq(group_to_ip(group));
+ }
+ break;
+ }
+ }
+
+ back_to_back_c0_hazard();
+ local_irq_restore(flags);
+}
+
+static unsigned int aruba_irq_startup(unsigned int irq)
+{
+ aruba_irq_enable(irq);
+ return 0;
+}
+
+#define aruba_irq_shutdown aruba_irq_disable
+
+static void aruba_irq_ack(unsigned int irq)
+{
+ aruba_irq_disable(irq);
+}
+
+static void aruba_irq_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ aruba_irq_enable(irq);
+}
+
+static struct hw_interrupt_type aruba_irq_type = {
+ .typename = "ARUBA",
+ .startup = aruba_irq_startup,
+ .shutdown = aruba_irq_shutdown,
+ .enable = aruba_irq_enable,
+ .disable = aruba_irq_disable,
+ .ack = aruba_irq_ack,
+ .end = aruba_irq_end,
+};
+
+void __init arch_init_irq(void)
+{
+ int i;
+ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
+ memset(irq_desc, 0, sizeof(irq_desc));
+
+ for (i = 0; i < RC32434_NR_IRQS; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].chip = &aruba_irq_type;
+ spin_lock_init(&irq_desc[i].lock);
+ }
+}
+
+/* Main Interrupt dispatcher */
+
+void plat_irq_dispatch(struct pt_regs *regs)
+{
+ unsigned int pend, group, ip;
+ volatile unsigned int *addr;
+ unsigned long cp0_cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
+
+ if (cp0_cause & CAUSEF_IP7)
+ return aruba_timer_interrupt(regs);
+
+ if(cp0_cause == 0) {
+ printk("INTERRUPT(S) FIRED WHILE MASKED\n");
+#ifdef ARUBA_DEBUG
+ // debuging use -- figure out which interrupt(s) fired
+ cp0_cause = read_c0_cause() & CAUSEF_IP;
+ while (cp0_cause) {
+ unsigned long intr_bit;
+ unsigned int irq_nr;
+ intr_bit = (31 - rc32434_clz(cp0_cause));
+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
+ printk(" ---> MASKED IRQ %d\n",irq_nr);
+ cp0_cause &= ~(1 << intr_bit);
+ }
+#endif
+ return;
+ }
+
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ if ((ip = (cp0_cause & 0x7c00))) {
+ group = 21 - rc32434_clz(ip);
+
+ addr = intr_group_muscat[group].base_addr;
+
+ pend = READ_PEND_MUSCAT(addr);
+ pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
+ pend = 39 - rc32434_clz(pend);
+ do_IRQ(pend + (group << 5));
+ }
+ break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
+ // Misc Interrupt
+ group = 0;
+
+ addr = intr_group_merlot[group].base_addr;
+
+ pend = READ_PEND_MERLOT(addr);
+ pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
+ pend = 31 - rc32434_clz(pend);
+ do_IRQ(pend + GROUP0_IRQ_BASE);
+ }
+ if ((ip = (cp0_cause & 0x3c00))) { // irq 2-5
+ pend = 31 - rc32434_clz(ip);
+ do_IRQ(pend - GROUP0_IRQ_BASE);
+ }
+ break;
+ }
+}

566
target/linux/aruba-2.6/patches/003-pci.patch
View file

@ -1,122 +1,3 @@
diff -Nur linux-2.6.15/arch/mips/pci/fixup-aruba.c linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c
--- linux-2.6.15/arch/mips/pci/fixup-aruba.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c 2006-01-10 00:34:41.000000000 +0100
@@ -0,0 +1,115 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI fixups for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h>
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+
+ if (dev->bus->number != 0) {
+ return 0;
+ }
+
+ slot = PCI_SLOT(dev->devfn);
+ dev->irq = 0;
+
+ if (slot > 0 && slot <= 15) {
+#if 1
+ if(slot == 10) {
+ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 9; // intA
+ } else if(slot == 11) {
+ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 10; // intA
+ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 10; // intA
+ if(pin == 3) dev->irq = GROUP4_IRQ_BASE + 10; // intA
+ } else if(slot == 12) {
+ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 11; // intA
+ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 12; // intB
+ } else if (slot == 13) {
+ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 12; // intA
+ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 11; // intB
+ } else {
+ dev->irq = GROUP4_IRQ_BASE + 11;
+ }
+#else
+ switch (pin) {
+ case 1: /* INTA*/
+ dev->irq = GROUP4_IRQ_BASE + 11;
+ break;
+ case 2: /* INTB */
+ dev->irq = GROUP4_IRQ_BASE + 11;
+ break;
+ case 3: /* INTC */
+ dev->irq = GROUP4_IRQ_BASE + 11;
+ break;
+ case 4: /* INTD */
+ dev->irq = GROUP4_IRQ_BASE + 11;
+ break;
+ default:
+ dev->irq = 0xff;
+ break;
+ }
+#endif
+#ifdef DEBUG
+ printk("irq fixup: slot %d, pin %d, irq %d\n",
+ slot, pin, dev->irq);
+#endif
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
+ }
+ return (dev->irq);
+}
+
+struct pci_fixup pcibios_fixups[] = {
+ {0}
+};
+
+
+
+
+
+
+
+
+
+
+
diff -Nur linux-2.6.15/arch/mips/pci/Makefile linux-2.6.15-openwrt/arch/mips/pci/Makefile
--- linux-2.6.15/arch/mips/pci/Makefile 2006-01-03 04:21:10.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/pci/Makefile 2006-01-10 00:32:32.000000000 +0100
@ -125,453 +6,6 @@ diff -Nur linux-2.6.15/arch/mips/pci/Makefile linux-2.6.15-openwrt/arch/mips/pci
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
+obj-$(CONFIG_MACH_ARUBA) += fixup-aruba.o ops-aruba.o pci-aruba.o
diff -Nur linux-2.6.15/arch/mips/pci/ops-aruba.c linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c
--- linux-2.6.15/arch/mips/pci/ops-aruba.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c 2006-01-10 00:32:32.000000000 +0100
@@ -0,0 +1,204 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * pci_ops for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+
+#define PCI_CFG_SET(slot,func,off) \
+ (rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
+ ((func)<<8) | (off)))
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+ unsigned int devfn, unsigned char where,
+ u32 * data)
+{
+ /*
+ * config cycles are on 4 byte boundary only
+ */
+ unsigned int slot = PCI_SLOT(devfn);
+ u8 func = PCI_FUNC(devfn);
+
+ if (slot < 2 || slot > 15) {
+ *data = 0xFFFFFFFF;
+ return -1;
+ }
+ /* Setup address */
+ PCI_CFG_SET(slot, func, where);
+ rc32434_sync();
+
+ if (access_type == PCI_ACCESS_WRITE) {
+ rc32434_sync();
+ rc32434_pci->pcicfgd = *data;
+ } else {
+ rc32434_sync();
+ *data = rc32434_pci->pcicfgd;
+ }
+
+ rc32434_sync();
+
+ return 0;
+}
+
+
+/*
+ * We can't address 8 and 16 bit words directly. Instead we have to
+ * read/write a 32bit word and mask/modify the data we actually want.
+ */
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 * val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 * val)
+{
+ u32 data;
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
+ return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 * val)
+{
+ int ret;
+
+ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+ return ret;
+}
+
+static int
+write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
+ u8 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
+ u16 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
+ u32 val)
+{
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 * val)
+{
+ switch (size) {
+ case 1:
+ return read_config_byte(bus, devfn, where, (u8 *) val);
+ case 2:
+ return read_config_word(bus, devfn, where, (u16 *) val);
+ default:
+ return read_config_dword(bus, devfn, where, val);
+ }
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ switch (size) {
+ case 1:
+ return write_config_byte(bus, devfn, where, (u8) val);
+ case 2:
+ return write_config_word(bus, devfn, where, (u16) val);
+ default:
+ return write_config_dword(bus, devfn, where, val);
+ }
+}
+
+struct pci_ops rc32434_pci_ops = {
+ .read = pci_config_read,
+ .write = pci_config_write,
+};
diff -Nur linux-2.6.15/arch/mips/pci/pci-aruba.c linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c
--- linux-2.6.15/arch/mips/pci/pci-aruba.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c 2006-01-10 00:32:32.000000000 +0100
@@ -0,0 +1,235 @@
+/**************************************************************************
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI initialization for IDT EB434 board
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ **************************************************************************
+ * May 2004 rkt, neb
+ *
+ * Initial Release
+ *
+ *
+ *
+ **************************************************************************
+ */
+
+#include <linux/autoconf.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/idt-boards/rc32434/rc32434.h>
+#include <asm/idt-boards/rc32434/rc32434_pci.h>
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+/* define an unsigned array for the PCI registers */
+unsigned int korinaCnfgRegs[25] = {
+ KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
+ KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
+ KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
+ KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
+ KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
+ KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
+};
+
+static struct resource rc32434_res_pci_mem2;
+
+static struct resource rc32434_res_pci_mem1 = {
+ .name = "PCI MEM1",
+ .start = 0x50000000,
+ .end = 0x5FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .child = &rc32434_res_pci_mem2,
+};
+static struct resource rc32434_res_pci_mem2 = {
+ .name = "PCI MEM2",
+ .start = 0x60000000,
+ .end = 0x6FFFFFFF,
+ .flags = IORESOURCE_MEM,
+ .parent = &rc32434_res_pci_mem1,
+};
+static struct resource rc32434_res_pci_io1 = {
+ .name = "PCI I/O1",
+ .start = 0x18800000,
+ .end = 0x188FFFFF,
+ .flags = IORESOURCE_IO,
+};
+
+extern struct pci_ops rc32434_pci_ops;
+
+struct pci_controller rc32434_controller = {
+ .pci_ops = &rc32434_pci_ops,
+ .mem_resource = &rc32434_res_pci_mem1,
+ .io_resource = &rc32434_res_pci_io1,
+ .mem_offset = 0x00000000UL,
+ .io_offset = 0x00000000UL,
+};
+
+extern unsigned int arch_has_pci;
+
+static int __init rc32434_pcibridge_init(void)
+{
+
+ unsigned int pciConfigAddr = 0;/*used for writing pci config values */
+ int loopCount=0 ;/*used for the loop */
+
+ unsigned int pcicValue, pcicData=0;
+ unsigned int dummyRead, pciCntlVal = 0;
+
+ if (!arch_has_pci) return 0;
+
+ printk("PCI: Initializing PCI\n");
+
+ /* Disable the IP bus error for PCI scaning */
+ pciCntlVal=rc32434_pci->pcic;
+ pciCntlVal &= 0xFFFFFF7;
+ rc32434_pci->pcic = pciCntlVal;
+
+ ioport_resource.start = rc32434_res_pci_io1.start;
+ ioport_resource.end = rc32434_res_pci_io1.end;
+/*
+ iomem_resource.start = rc32434_res_pci_mem1.start;
+ iomem_resource.end = rc32434_res_pci_mem1.end;
+*/
+
+ pcicValue = rc32434_pci->pcic;
+ pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
+ if (!((pcicValue == PCIM_H_EA) ||
+ (pcicValue == PCIM_H_IA_FIX) ||
+ (pcicValue == PCIM_H_IA_RR))) {
+ /* Not in Host Mode, return ERROR */
+ return -1;
+ }
+
+ /* Enables the Idle Grant mode, Arbiter Parking */
+ pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
+ rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
+ /* Zero out the PCI status & PCI Status Mask */
+ for(;;) {
+ pcicData = rc32434_pci->pcis;
+ if (!(pcicData & PCIS_rip_m))
+ break;
+ }
+
+ rc32434_pci->pcis = 0;
+ rc32434_pci->pcism = 0xFFFFFFFF;
+ /* Zero out the PCI decoupled registers */
+ rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
+ rc32434_pci->pcidas=0; /* clear the status */
+ rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
+ /* Mask PCI Messaging Interrupts */
+ rc32434_pci_msg->pciiic = 0;
+ rc32434_pci_msg->pciiim = 0xFFFFFFFF;
+ rc32434_pci_msg->pciioic = 0;
+ rc32434_pci_msg->pciioim = 0;
+
+ /* Setup PCILB0 as Memory Window */
+ rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
+
+ /* setup the PCI map address as same as the local address */
+
+ rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
+
+ /* Setup PCILBA1 as MEM */
+#ifdef __MIPSEB__
+ rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+ rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
+#endif
+ dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
+
+ rc32434_pci->pcilba[1].a = 0x60000000;
+
+ rc32434_pci->pcilba[1].m = 0x60000000;
+ /* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+ rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+ rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
+#endif
+ dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
+ rc32434_pci->pcilba[2].a = 0x18C00000;
+
+ rc32434_pci->pcilba[2].m = 0x18FFFFFF;
+ /* setup PCILBA2 as IO Window*/
+#ifdef __MIPSEB__
+ rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
+#else
+ rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
+#endif
+
+ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
+
+
+ rc32434_pci->pcilba[3].a = 0x18800000;
+
+ rc32434_pci->pcilba[3].m = 0x18800000;
+ /* Setup PCILBA3 as IO Window */
+
+#ifdef __MIPSEB__
+ rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCILBAC_sb_m);
+#else
+ rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
+#endif
+ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
+
+ pciConfigAddr = (unsigned int)(0x80000004);
+ for(loopCount = 0; loopCount < 24; loopCount++){
+ rc32434_pci->pcicfga = pciConfigAddr;
+ dummyRead = rc32434_pci->pcicfga;
+ rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
+ dummyRead=rc32434_pci->pcicfgd;
+ pciConfigAddr += 4;
+ }
+ rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
+ ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
+
+ pciCntlVal = rc32434_pci->pcic;
+ pciCntlVal &= ~(PCIC_tnr_m);
+ rc32434_pci->pcic = pciCntlVal;
+ pciCntlVal = rc32434_pci->pcic;
+
+ register_pci_controller(&rc32434_controller);
+
+ rc32434_sync();
+ return 0;
+}
+
+arch_initcall(rc32434_pcibridge_init);
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
diff -Nur linux-2.6.15/drivers/pci/access.c linux-2.6.15-openwrt/drivers/pci/access.c
--- linux-2.6.15/drivers/pci/access.c 2006-01-03 04:21:10.000000000 +0100
+++ linux-2.6.15-openwrt/drivers/pci/access.c 2006-01-10 00:43:10.000000000 +0100

114
target/linux/aruba-2.6/patches/004-wdt.patch
View file

@ -1,117 +1,3 @@
diff -Nur linux-2.6.15.1/drivers/char/watchdog/wdt_merlot.c linux-2.6.15.1-openwrt/drivers/char/watchdog/wdt_merlot.c
--- linux-2.6.15.1/drivers/char/watchdog/wdt_merlot.c 2006-01-26 21:14:02.204626250 -0800
+++ linux-2.6.15.1-openwrt/drivers/char/watchdog/wdt_merlot.c 2006-02-02 20:31:43.000000000 -0800
@@ -0,0 +1,110 @@
+#include <linux/autoconf.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/fs.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/bootinfo.h>
+
+extern unsigned long mips_machtype;
+
+static unsigned long wdt_is_open;
+static struct timer_list wdt_timer;
+
+static void wdt_merlot_refresh(void)
+{
+ volatile __u32 *wdt;
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ wdt = (__u32 *) 0xb8030034;
+ *wdt = 0x10000000;
+ break;
+ default:
+ wdt = (__u32 *) 0xbc00300c;
+ *wdt = 0x40000000;
+ break;
+ }
+}
+
+static void wdt_merlot_timer_fn(unsigned long data)
+{
+ wdt_merlot_refresh();
+ if (!test_bit(1, &wdt_is_open))
+ mod_timer(&wdt_timer, jiffies + HZ);
+}
+
+static int wdt_merlot_setup_timer(void)
+{
+
+ init_timer(&wdt_timer);
+ wdt_timer.function = wdt_merlot_timer_fn;
+ wdt_timer.data = 0;
+ wdt_timer.expires = jiffies + HZ;
+ add_timer(&wdt_timer);
+ return 0;
+}
+
+static int wdt_open(struct inode *inode, struct file *file)
+{
+ if (test_and_set_bit(0, &wdt_is_open))
+ return -EBUSY;
+ set_bit(1, &wdt_is_open);
+ return nonseekable_open(inode, file);
+}
+
+static ssize_t wdt_write(struct file *file, const char __user * buf, size_t count, loff_t * ppos)
+{
+ if (count) /* something was written */
+ wdt_merlot_refresh();
+ return count;
+}
+
+static int wdt_release(struct inode *inode, struct file *file)
+{
+ clear_bit(0, &wdt_is_open);
+ return 0;
+}
+
+static struct file_operations wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = wdt_write,
+ .open = wdt_open,
+ .release = wdt_release,
+};
+
+static struct miscdevice wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &wdt_fops,
+};
+
+static void __exit wdt_exit(void)
+{
+ misc_deregister(&wdt_miscdev);
+}
+
+static int __init wdt_init(void)
+{
+ int ret;
+ ret = misc_register(&wdt_miscdev);
+ if (ret) {
+ printk(KERN_ERR
+ "wdt: cannot register miscdev on minor=%d (err=%d)\n",
+ WATCHDOG_MINOR, ret);
+ misc_deregister(&wdt_miscdev);
+ goto out;
+ }
+ printk("wdt: registered with refresh\n");
+ wdt_merlot_refresh();
+ wdt_merlot_setup_timer();
+ out:
+ return ret;
+}
+
+module_init(wdt_init);
+module_exit(wdt_exit);
diff -Nur linux-2.6.15.3/drivers/char/watchdog/Makefile linux-2.6.15.3-openwrt/drivers/char/watchdog/Makefile
--- linux-2.6.15.3/drivers/char/watchdog/Makefile 2006-02-22 10:04:18.596278000 -0800
+++ linux-2.6.15.3-openwrt/drivers/char/watchdog/Makefile 2006-02-22 10:06:21.400960000 -0800

2148
target/linux/aruba-2.6/patches/010-ar2313_enet.patch
View file

File diff suppressed because it is too large Load diff