openwrtv4/target/linux/imx6/patches-3.10/110-gw5400-a.patch

--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard.dtb \
 	imx6q-arm2.dtb \
+	imx6q-gw5400-a.dtb \
 	imx6q-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -98,6 +98,14 @@
 							MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
 						>;
 					};
+
+					pinctrl_audmux_3: audmux-3 {
+						fsl,pins = <
+							MX6Q_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
+							MX6Q_PAD_EIM_D25__AUD5_RXC      0x80000000
+							MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
+						>;
+					};
 				};
 
 				ecspi1 {
@@ -187,6 +195,30 @@
 							MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
 						>;
 					};
+
+					/* No strobe */
+					pinctrl_gpmi_nand_2: gpmi-nand-2 {
+						fsl,pins = <
+							MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+							MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+							MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+							MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
+							MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+							MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+							MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
+							MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
+							MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+							MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+							MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+							MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+							MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+							MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+							MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+							MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+							MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+							MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+						>;
+					};
 				};
 
 				i2c1 {
@@ -205,6 +237,12 @@
 							MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 						>;
 					};
+					pinctrl_i2c2_2: i2c2grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+							MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+						>;
+					};
 				};
 
 				i2c3 {
@@ -214,6 +252,12 @@
 							MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 						>;
 					};
+					pinctrl_i2c3_2: i2c3grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+							MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+						>;
+					};
 				};
 
 				uart1 {
@@ -223,6 +267,12 @@
 							MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 						>;
 					};
+					pinctrl_uart1_2: uart1grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+							MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+						>;
+					};
 				};
 
 				uart2 {
@@ -232,6 +282,21 @@
 							MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 						>;
 					};
+					pinctrl_uart2_2: uart2grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+							MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+						>;
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3_1: uart3grp-1 {
+						fsl,pins = <
+							MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
+							MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
+						>;
+					};
 				};
 
 				uart4 {
@@ -242,6 +307,15 @@
 						>;
 					};
 				};
+
+				uart5 {
+					pinctrl_uart5_1: uart5grp-1 {
+						fsl,pins = <
+							MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+							MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+						>;
+					};
+				};
 
 				usbotg {
 					pinctrl_usbotg_1: usbotggrp-1 {
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -25,6 +25,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/opp.h>
+#include <linux/pci.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
@@ -145,6 +146,38 @@ static void __init imx6q_sabrelite_init(
 	imx6q_sabrelite_cko1_setup();
 }
 
+/*
+ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
+ * as they are used for slots1-7 PERST#
+ */
+static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
+{
+	u32 dw;
+
+	if (!of_machine_is_compatible("gw,ventana"))
+		return;
+
+	if (dev->devfn != 0)
+		return;
+
+	pci_read_config_dword(dev, 0x62c, &dw);
+	dw |= 0xaaa8; // GPIO1-7 outputs
+	pci_write_config_dword(dev, 0x62c, dw);
+
+	pci_read_config_dword(dev, 0x644, &dw);
+	dw |= 0xfe;   // GPIO1-7 output high
+	pci_write_config_dword(dev, 0x644, dw);
+
+	mdelay(1);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
+	mx6_ventana_pciesw_early_fixup);
+
+static void __init imx6q_ventana_init(void)
+{
+	imx6q_sabrelite_cko1_setup();
+}
+
 static void __init imx6q_1588_init(void)
 {
 	struct regmap *gpr;
@@ -163,6 +196,9 @@ static void __init imx6q_usb_init(void)
 
 static void __init imx6q_init_machine(void)
 {
+	if (of_machine_is_compatible("gw,ventana"))
+		imx6q_ventana_init();
+
 	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 		imx6q_sabrelite_init();