2013-09-20 01:59:32 +00:00
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From: Sean Cross <xobs@kosagi.com>
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2013-10-03 13:06:42 +00:00
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Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition
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2013-09-20 01:59:32 +00:00
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PCIe requires additional bits be defined for GPR8 and GPR12.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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2013-10-03 13:06:42 +00:00
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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2013-09-20 01:59:32 +00:00
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---
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2013-10-03 13:06:42 +00:00
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include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
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2013-09-20 01:59:32 +00:00
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1 file changed, 8 insertions(+)
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--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@@ -241,6 +241,12 @@
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#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
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+#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
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+#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
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+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
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+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
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+#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
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+
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#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
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#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
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@@ -273,7 +279,9 @@
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#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
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#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
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#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
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+#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
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#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
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+#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
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#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
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#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
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