imx6: update upstream pcie patches
Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 38298
This commit is contained in:
parent
5617993e10
commit
60dd4429b7
16 changed files with 130 additions and 118 deletions
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@ -1,6 +1,4 @@
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From 20a677fd63c57edd5b0c463baa44f133b2f2d4a0 Mon Sep 17 00:00:00 2001
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From: Peter Chen <peter.chen@freescale.com>
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Date: Thu, 13 Jun 2013 17:59:52 +0300
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Subject: [PATCH] usb: chipidea: improve kconfig
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Randy Dunlap <rdunlap@infradead.org> reported this problem
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@ -1,6 +1,4 @@
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From 972a6c5d56b42d6dd326867d5974ffa58383ec53 Mon Sep 17 00:00:00 2001
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From: Peter Chen <peter.chen@freescale.com>
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Date: Mon, 29 Jul 2013 13:09:57 +0300
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Subject: [PATCH] usb: chipidea: fix the build error with randconfig
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Using below configs, the compile will have error:
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@ -1,6 +1,4 @@
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From a0cfdc6bc73bc47b63b05b850cf66cf67f2487bf Mon Sep 17 00:00:00 2001
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From: Lothar Waßmann <LW@KARO-electronics.de>
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Date: Wed, 14 Aug 2013 12:43:58 +0300
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Subject: [PATCH] usb: chipidea: improve kconfig 2.0
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This patch provides a cleaner solution to the problem described in
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@ -1,6 +1,4 @@
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From 0d1ee1f265cf9730feb214ddd18bc430c0800e8b Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Tue, 10 Sep 2013 21:42:29 +0200
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Subject: [PATCH] i2c: imx: retry on NAK
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In case of busy i2c try again to get ACK.
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@ -1,6 +1,4 @@
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From 9e54eae23bc9cca0d8a955018c35b1250e09a73a Mon Sep 17 00:00:00 2001
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From: Richard Zhu <r65037@freescale.com>
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Date: Wed, 24 Jul 2013 14:15:29 +0800
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Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms
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imx6q contains one Synopsys AHCI SATA controller, But it can't share
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@ -1,6 +1,4 @@
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From 6a6c21ef487be47b300a0b24cd6afeb69d8b9a1a Mon Sep 17 00:00:00 2001
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From: Richard Zhu <r65037@freescale.com>
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Date: Wed, 24 Jul 2013 14:15:28 +0800
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Subject: [PATCH] ARM: imx6q: update the sata bits definitions of gpr13
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Replace the SATA_PHY_# by the more readable definitons.
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@ -1,6 +1,4 @@
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From 0fb1f804269e549b556b475c8655bc862c220622 Mon Sep 17 00:00:00 2001
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From: Richard Zhu <r65037@freescale.com>
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Date: Tue, 16 Jul 2013 11:28:46 +0800
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Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms
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Only imx6q has the ahci sata controller, enable
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@ -1,6 +1,4 @@
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From 867974fc09f93bdd7f98d46ac3733934486bbf4a Mon Sep 17 00:00:00 2001
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From: Tejun Heo <tj@kernel.org>
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Date: Fri, 26 Jul 2013 08:57:56 -0400
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Subject: [PATCH] ahci_imx: depend on CONFIG_MFD_SYSCON
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ahci_imx makes use of regmap but the dependency wasn't specified in
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@ -1,11 +1,13 @@
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Subject: [v6,2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition
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From: Sean Cross <xobs@kosagi.com>
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Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition
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PCIe requires additional bits be defined for GPR8 and GPR12.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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---
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include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
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include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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@ -1,79 +1,28 @@
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Subject: [v6,3/3] PCI: imx6: Add support for i.MX6 PCIe controller
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Subject: [PATCH 2/2] PCI: imx6: Add support for i.MX6 PCIe controller
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From: Sean Cross <xobs@kosagi.com>
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Add support for the PCIe port present on the i.MX6 family of controllers.
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These use the Synopsis Designware core tied to their own PHY.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
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---
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arch/arm/boot/dts/imx6qdl.dtsi | 16 +
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arch/arm/mach-imx/Kconfig | 2 +
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arch/arm/mach-imx/clk-imx6q.c | 4 +
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drivers/pci/host/Kconfig | 6 +
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drivers/pci/host/Makefile | 1 +
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drivers/pci/host/pci-imx6.c | 576 ++++++++++++++++++++
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7 files changed, 611 insertions(+), 1 deletion(-)
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drivers/pci/host/Kconfig | 6 +
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drivers/pci/host/Makefile | 1 +
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drivers/pci/host/pci-imx6.c | 575 +++++++++++++++++++++
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4 files changed, 588 insertions(+), 1 deletion(-)
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create mode 100644 drivers/pci/host/pci-imx6.c
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--- a/arch/arm/boot/dts/imx6qdl.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl.dtsi
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@@ -108,6 +108,22 @@
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cache-level = <2>;
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};
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+ pcie: pcie@0x01000000 {
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+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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+ reg = <0x01ffc000 0x4000>; /* DBI */
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
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+ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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+ num-lanes = <1>;
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+ interrupts = <0 123 0x04>;
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+ clocks = <&clks 189>, <&clks 187>, <&clks 205>, <&clks 144>;
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+ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
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+ status = "disabled";
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+ };
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+
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 94 0x04>;
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--- a/arch/arm/mach-imx/Kconfig
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+++ b/arch/arm/mach-imx/Kconfig
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@@ -806,6 +806,8 @@ config SOC_IMX6Q
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select HAVE_IMX_SRC
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select HAVE_SMP
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select MFD_SYSCON
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+ select MIGHT_HAVE_PCI
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+ select PCI_DOMAINS if PCI
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select PINCTRL
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select PINCTRL_IMX6Q
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select PL310_ERRATA_588369 if CACHE_PL310
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void)
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clk_prepare_enable(clk[usbphy2_gate]);
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}
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+ /* All existing boards with PCIe use LVDS1 */
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+ if (IS_ENABLED(CONFIG_PCI_IMX6))
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+ clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
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+
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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--- /dev/null
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+++ b/drivers/pci/host/Kconfig
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@@ -0,0 +1,13 @@
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+menu "PCI host controller drivers"
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+ depends on PCI
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+ depends on PCI
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+
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+config PCIE_DW
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+ bool
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+ bool
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+
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+config PCI_IMX6
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+ bool "Freescale i.MX6 PCIe controller"
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+obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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--- /dev/null
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -0,0 +1,576 @@
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@@ -0,0 +1,575 @@
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+/*
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+ * PCIe host controller driver for Freescale i.MX6 SoCs
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+ *
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+ return 0;
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+
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+ udelay(1);
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+ } while ((wait_counter < max_iterations) && (val != exp_val));
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+ } while (wait_counter < max_iterations);
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+
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+ return -ETIMEDOUT;
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+}
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+ var = data << PCIE_PHY_CTRL_DATA_LOC;
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+ writel(var, dbi_base + PCIE_PHY_CTRL);
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+
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+ /* wait for ack de-assetion */
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+ /* wait for ack de-assertion */
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+ ret = pcie_phy_poll_ack(dbi_base, 0);
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+ if (ret)
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+ return ret;
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+ var = data << PCIE_PHY_CTRL_DATA_LOC;
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+ writel(var, dbi_base + PCIE_PHY_CTRL);
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+
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+ /* wait for ack de-assetion */
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+ /* wait for ack de-assertion */
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+ ret = pcie_phy_poll_ack(dbi_base, 0);
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+ if (ret)
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+ return ret;
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+ if (ltssm != 0x0d)
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+ return 0;
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+
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+ dev_err(pp->dev,
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+ "transition to gen2 is stuck, reset PHY!\n");
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+ dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
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+
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+ pcie_phy_read(pp->dbi_base,
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+ PHY_RX_OVRD_IN_LO, &temp);
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+ }
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+
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+ /* Fetch clocks */
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+ imx6_pcie->lvds_gate = clk_get(&pdev->dev, "lvds_gate");
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+ imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
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+ if (IS_ERR(imx6_pcie->lvds_gate)) {
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+ dev_err(&pdev->dev,
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+ "lvds_gate clock select missing or invalid\n");
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+ goto err;
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+ }
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+
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+ imx6_pcie->sata_ref_100m = clk_get(&pdev->dev, "sata_ref_100m");
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+ imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
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+ if (IS_ERR(imx6_pcie->sata_ref_100m)) {
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+ dev_err(&pdev->dev,
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+ "sata_ref_100m clock source missing or invalid\n");
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+ goto err;
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+ }
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+
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+ imx6_pcie->pcie_ref_125m = clk_get(&pdev->dev, "pcie_ref_125m");
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+ imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
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+ if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
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+ dev_err(&pdev->dev,
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+ "pcie_ref_125m clock source missing or invalid\n");
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+ goto err;
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+ }
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+
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+ imx6_pcie->pcie_axi = clk_get(&pdev->dev, "pcie_axi");
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+ imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
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+ if (IS_ERR(imx6_pcie->pcie_axi)) {
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+ dev_err(&pdev->dev,
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+ "pcie_axi clock source missing or invalid\n");
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+
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+/* Freescale PCIe driver does not allow module unload */
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+
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+static int __init imx6_init(void)
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+static int __init imx6_pcie_init(void)
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+{
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+ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
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+}
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+module_init(imx6_init);
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+module_init(imx6_pcie_init);
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+
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+MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
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+MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
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Subject: [v6,1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
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From: Sean Cross <xobs@kosagi.com>
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Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
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The i.MX6 has two general-purpose LVDS clocks that can be driven
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from a variety of sources. This patch adds a mux and a gate for
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both of these clocks.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++-
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.../devicetree/bindings/clock/imx6q-clock.txt | 4 ++++
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arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++-
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2 files changed, 23 insertions(+), 1 deletion(-)
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--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
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+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
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@@ -208,6 +208,10 @@ clocks and IDs.
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pll4_post_div 193
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pll5_post_div 194
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pll5_video_div 195
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+ lvds1_sel 204
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+ lvds2_sel 205
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+ lvds1_gate 206
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+ lvds2_gate 207
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Examples:
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a
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@ -0,0 +1,38 @@
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From 4f6723e8ff497e35c8f2fb20886fccc533c58cdb Mon Sep 17 00:00:00 2001
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From: Sean Cross <xobs@kosagi.com>
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Date: Thu, 26 Sep 2013 10:45:35 +0800
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Subject: [PATCH] ARM: imx6q: clock and Kconfig update for PCIe support
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Update imx6q clock initialization and Kconfig for PCIe support.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/Kconfig | 2 ++
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arch/arm/mach-imx/clk-imx6q.c | 4 ++++
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2 files changed, 6 insertions(+)
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--- a/arch/arm/mach-imx/Kconfig
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+++ b/arch/arm/mach-imx/Kconfig
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@@ -806,6 +806,8 @@ config SOC_IMX6Q
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select HAVE_IMX_SRC
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select HAVE_SMP
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select MFD_SYSCON
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+ select MIGHT_HAVE_PCI
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+ select PCI_DOMAINS if PCI
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select PINCTRL
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select PINCTRL_IMX6Q
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select PL310_ERRATA_588369 if CACHE_PL310
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void)
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clk_prepare_enable(clk[usbphy2_gate]);
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}
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+ /* All existing boards with PCIe use LVDS1 */
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+ if (IS_ENABLED(CONFIG_PCI_IMX6))
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+ clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
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+
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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@ -0,0 +1,38 @@
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From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001
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From: Sean Cross <xobs@kosagi.com>
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Date: Thu, 26 Sep 2013 10:51:09 +0800
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Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node
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Add pcie device node for imx6qdl.
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Signed-off-by: Sean Cross <xobs@kosagi.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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--- a/arch/arm/boot/dts/imx6qdl.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl.dtsi
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@@ -108,6 +108,22 @@
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cache-level = <2>;
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};
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+ pcie: pcie@0x01000000 {
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+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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+ reg = <0x01ffc000 0x4000>; /* DBI */
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
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+ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
|
||||
+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||
+ num-lanes = <1>;
|
||||
+ interrupts = <0 123 0x04>;
|
||||
+ clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
||||
+ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 94 0x04>;
|
|
@ -25,9 +25,6 @@ Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
|
|||
create mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.txt
|
||||
create mode 100644 drivers/thermal/imx_thermal.c
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
|
||||
new file mode 100644
|
||||
index 0000000..541c25e
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
|
||||
@@ -0,0 +1,17 @@
|
||||
|
@ -48,8 +45,6 @@ index 0000000..541c25e
|
|||
+ fsl,tempmon = <&anatop>;
|
||||
+ fsl,tempmon-data = <&ocotp>;
|
||||
+};
|
||||
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
|
||||
index e988c81..69eed55 100644
|
||||
--- a/drivers/thermal/Kconfig
|
||||
+++ b/drivers/thermal/Kconfig
|
||||
@@ -91,6 +91,17 @@ config THERMAL_EMULATION
|
||||
|
@ -70,21 +65,16 @@ index e988c81..69eed55 100644
|
|||
config SPEAR_THERMAL
|
||||
bool "SPEAr thermal sensor driver"
|
||||
depends on PLAT_SPEAR
|
||||
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
|
||||
index 67184a2..dff19c6 100644
|
||||
--- a/drivers/thermal/Makefile
|
||||
+++ b/drivers/thermal/Makefile
|
||||
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_thermal.o
|
||||
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_t
|
||||
obj-$(CONFIG_DOVE_THERMAL) += dove_thermal.o
|
||||
obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
|
||||
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
|
||||
+obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
|
||||
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
|
||||
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
|
||||
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
|
||||
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
|
||||
new file mode 100644
|
||||
index 0000000..d16c33c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/drivers/thermal/imx_thermal.c
|
||||
@@ -0,0 +1,397 @@
|
||||
|
@ -485,6 +475,3 @@ index 0000000..d16c33c
|
|||
+MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_ALIAS("platform:imx-thermal");
|
||||
--
|
||||
1.8.4
|
||||
|
||||
|
|
|
@ -1,3 +1,14 @@
|
|||
--- a/arch/arm/boot/dts/imx6qdl.dtsi
|
||||
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
|
||||
@@ -119,7 +119,7 @@
|
||||
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
interrupts = <0 123 0x04>;
|
||||
- clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
||||
+ clocks = <&clks 189>, <&clks 187>, <&clks 198>, <&clks 144>;
|
||||
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
status = "disabled";
|
||||
};
|
||||
--- a/drivers/pci/Kconfig
|
||||
+++ b/drivers/pci/Kconfig
|
||||
@@ -125,3 +125,5 @@ config PCI_IOAPIC
|
||||
|
|
|
@ -1,14 +1,3 @@
|
|||
--- a/arch/arm/boot/dts/imx6qdl.dtsi
|
||||
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
|
||||
@@ -119,7 +119,7 @@
|
||||
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
interrupts = <0 123 0x04>;
|
||||
- clocks = <&clks 189>, <&clks 187>, <&clks 205>, <&clks 144>;
|
||||
+ clocks = <&clks 189>, <&clks 187>, <&clks 198>, <&clks 144>;
|
||||
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
status = "disabled";
|
||||
};
|
||||
--- a/drivers/pci/host/pci-imx6.c
|
||||
+++ b/drivers/pci/host/pci-imx6.c
|
||||
@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *
|
||||
|
|
Loading…
Reference in a new issue