111 lines
2.9 KiB
Diff
111 lines
2.9 KiB
Diff
|
From 840202d23892baaff74be11ec71c3ffc6ad6298e Mon Sep 17 00:00:00 2001
|
||
|
|
From: Tim Harvey <tharvey@gateworks.com>
|
||
|
|
Date: Tue, 20 Jan 2015 08:46:55 -0800
|
||
|
|
Subject: [PATCH] ARM: dts: imx6 ventana: Add PCI nodes for on-board PCI
|
||
|
|
devices
|
||
|
|
|
||
|
|
If the PCI nodes are defined, drivers can access information from the DT.
|
||
|
|
For example, the sky2 enet driver can obtain the mac address configured
|
||
|
|
from the bootloader (which is applied to the DT node with the ethernet1 alias).
|
||
|
|
|
||
|
|
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
||
|
|
---
|
||
|
|
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
|
||
|
|
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
|
||
|
|
2 files changed, 72 insertions(+), 4 deletions(-)
|
||
|
|
|
||
|
|
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
|
||
|
|
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
|
||
|
|
@@ -280,8 +280,42 @@
|
||
|
|
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
|
||
|
|
- compatible = "marvell,sky2";
|
||
|
|
+ pcie@0,0 {
|
||
|
|
+ /* 00:00.0 0604: 16c3:abcd root host-bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ pcie@0,0 {
|
||
|
|
+ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * GigE PCI dev node needs to be defined so that enet
|
||
|
|
+ * driver can use it to obtain its boot-loader
|
||
|
|
+ * specified MAC
|
||
|
|
+ */
|
||
|
|
+ pcie@4,0 {
|
||
|
|
+ /* 02:04.0 0604: 10b5:8609: PEX port bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x2000 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ eth1: pci@0,0 {
|
||
|
|
+ /* 04:00.0 0200: 11ab:4380: GigE */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+ compatible = "marvell,sky2";
|
||
|
|
+ };
|
||
|
|
+ };
|
||
|
|
+ };
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
|
||
|
|
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
|
||
|
|
@@ -369,8 +369,42 @@
|
||
|
|
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
|
||
|
|
- compatible = "marvell,sky2";
|
||
|
|
+ pcie@0,0 {
|
||
|
|
+ /* 00:00.0 0604: 16c3:abcd root host-bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ pcie@0,0 {
|
||
|
|
+ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ /*
|
||
|
|
+ * GigE PCI dev node needs to be defined so that enet
|
||
|
|
+ * driver can use it to obtain its boot-loader
|
||
|
|
+ * specified MAC
|
||
|
|
+ */
|
||
|
|
+ pcie@8,0 {
|
||
|
|
+ /* 02:08.0 0604: 10b5:8609: PEX port bridge */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x4000 0 0 0 0>;
|
||
|
|
+
|
||
|
|
+ eth1: pci@0,0 {
|
||
|
|
+ /* 08:00.0 0200: 11ab:4380: GigE */
|
||
|
|
+ #address-cells = <3>;
|
||
|
|
+ #size-cells = <2>;
|
||
|
|
+ device_type = "pci";
|
||
|
|
+ reg = <0x0 0 0 0 0>;
|
||
|
|
+ compatible = "marvell,sky2";
|
||
|
|
+ };
|
||
|
|
+ };
|
||
|
|
+ };
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|