59 lines
1.9 KiB
Diff
59 lines
1.9 KiB
Diff
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From c1d35c42d697e9c28c817921a79c5f814529a4c6 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 14 Apr 2013 09:55:29 +0200
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Subject: [PATCH 126/137] MIPS: ralink: add memory definition for MT7620
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Populate struct soc_info with the data that describes our RAM window.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5183/
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---
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arch/mips/include/asm/mach-ralink/mt7620.h | 8 ++++++++
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arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++
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2 files changed, 28 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -50,6 +50,14 @@
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#define SYSCFG0_DRAM_TYPE_DDR1 1
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#define SYSCFG0_DRAM_TYPE_DDR2 2
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+#define MT7620_DRAM_BASE 0x0
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+#define MT7620_SDRAM_SIZE_MIN 2
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+#define MT7620_SDRAM_SIZE_MAX 64
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+#define MT7620_DDR1_SIZE_MIN 32
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+#define MT7620_DDR1_SIZE_MAX 128
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+#define MT7620_DDR2_SIZE_MIN 32
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+#define MT7620_DDR2_SIZE_MAX 256
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+
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#define MT7620_GPIO_MODE_I2C BIT(0)
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#define MT7620_GPIO_MODE_UART0_SHIFT 2
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#define MT7620_GPIO_MODE_UART0_MASK 0x7
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_inf
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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+
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+ switch (dram_type) {
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+ case SYSCFG0_DRAM_TYPE_SDRAM:
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+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
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+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
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+ break;
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+
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+ case SYSCFG0_DRAM_TYPE_DDR1:
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+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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+ break;
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+
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+ case SYSCFG0_DRAM_TYPE_DDR2:
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+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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+ break;
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+ default:
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+ BUG();
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+ }
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+ soc_info->mem_base = MT7620_DRAM_BASE;
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}
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