ramips: sync kernel patches with the mips-next tree
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 36431
This commit is contained in:
parent
831c7ea04f
commit
deb3635923
58 changed files with 1984 additions and 3231 deletions
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@ -0,0 +1,154 @@
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From dd4bb7e821d112bff981016fd4e7c014ca9425f9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 11 Apr 2013 05:34:59 +0000
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Subject: [PATCH 100/137] MIPS: move mips_{set,get}_machine_name() to a more
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generic place
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Previously this functionality was only available to users of the mips_machine
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api. Moving the code to prom.c allows us to also add a OF wrapper.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5164/
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---
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arch/mips/include/asm/mips_machine.h | 4 ----
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arch/mips/include/asm/prom.h | 3 +++
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arch/mips/kernel/mips_machine.c | 21 ---------------------
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arch/mips/kernel/proc.c | 2 +-
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arch/mips/kernel/prom.c | 31 +++++++++++++++++++++++++++++++
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5 files changed, 35 insertions(+), 26 deletions(-)
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--- a/arch/mips/include/asm/mips_machine.h
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+++ b/arch/mips/include/asm/mips_machine.h
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@@ -42,13 +42,9 @@ extern long __mips_machines_end;
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#ifdef CONFIG_MIPS_MACHINE
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int mips_machtype_setup(char *id) __init;
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void mips_machine_setup(void) __init;
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-void mips_set_machine_name(const char *name) __init;
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-char *mips_get_machine_name(void);
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#else
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static inline int mips_machtype_setup(char *id) { return 1; }
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static inline void mips_machine_setup(void) { }
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-static inline void mips_set_machine_name(const char *name) { }
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-static inline char *mips_get_machine_name(void) { return NULL; }
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#endif /* CONFIG_MIPS_MACHINE */
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#endif /* __ASM_MIPS_MACHINE_H */
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--- a/arch/mips/include/asm/prom.h
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+++ b/arch/mips/include/asm/prom.h
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@@ -48,4 +48,7 @@ extern void __dt_setup_arch(struct boot_
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static inline void device_tree_init(void) { }
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#endif /* CONFIG_OF */
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+extern char *mips_get_machine_name(void);
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+extern void mips_set_machine_name(const char *name);
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+
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#endif /* __ASM_PROM_H */
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--- a/arch/mips/kernel/mips_machine.c
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+++ b/arch/mips/kernel/mips_machine.c
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@@ -13,7 +13,6 @@
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#include <asm/mips_machine.h>
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static struct mips_machine *mips_machine __initdata;
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-static char *mips_machine_name = "Unknown";
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#define for_each_machine(mach) \
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for ((mach) = (struct mips_machine *)&__mips_machines_start; \
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@@ -21,25 +20,6 @@ static char *mips_machine_name = "Unknow
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(unsigned long)(mach) < (unsigned long)&__mips_machines_end; \
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(mach)++)
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-__init void mips_set_machine_name(const char *name)
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-{
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- char *p;
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-
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- if (name == NULL)
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- return;
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-
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- p = kstrdup(name, GFP_KERNEL);
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- if (!p)
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- pr_err("MIPS: no memory for machine_name\n");
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-
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- mips_machine_name = p;
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-}
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-
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-char *mips_get_machine_name(void)
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-{
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- return mips_machine_name;
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-}
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-
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__init int mips_machtype_setup(char *id)
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{
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struct mips_machine *mach;
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@@ -79,7 +59,6 @@ __init void mips_machine_setup(void)
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return;
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mips_set_machine_name(mips_machine->mach_name);
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- pr_info("MIPS: machine is %s\n", mips_machine_name);
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if (mips_machine->mach_setup)
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mips_machine->mach_setup();
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--- a/arch/mips/kernel/proc.c
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+++ b/arch/mips/kernel/proc.c
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@@ -12,7 +12,7 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsregs.h>
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#include <asm/processor.h>
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-#include <asm/mips_machine.h>
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+#include <asm/prom.h>
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unsigned int vced_count, vcei_count;
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--- a/arch/mips/kernel/prom.c
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+++ b/arch/mips/kernel/prom.c
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@@ -23,6 +23,22 @@
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#include <asm/page.h>
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#include <asm/prom.h>
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+static char mips_machine_name[64] = "Unknown";
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+
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+__init void mips_set_machine_name(const char *name)
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+{
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+ if (name == NULL)
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+ return;
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+
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+ strncpy(mips_machine_name, name, sizeof(mips_machine_name));
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+ pr_info("MIPS: machine is %s\n", mips_get_machine_name());
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+}
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+
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+char *mips_get_machine_name(void)
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+{
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+ return mips_machine_name;
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+}
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+
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int __init early_init_dt_scan_memory_arch(unsigned long node,
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const char *uname, int depth,
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void *data)
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@@ -50,6 +66,18 @@ void __init early_init_dt_setup_initrd_a
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}
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#endif
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+int __init early_init_dt_scan_model(unsigned long node, const char *uname,
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+ int depth, void *data)
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+{
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+ if (!depth) {
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+ char *model = of_get_flat_dt_prop(node, "model", NULL);
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+
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+ if (model)
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+ mips_set_machine_name(model);
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+ }
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+ return 0;
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+}
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+
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void __init early_init_devtree(void *params)
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{
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/* Setup flat device-tree pointer */
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@@ -65,6 +93,9 @@ void __init early_init_devtree(void *par
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/* Scan memory nodes */
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of_scan_flat_dt(early_init_dt_scan_root, NULL);
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of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
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+
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+ /* try to load the mips machine name */
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+ of_scan_flat_dt(early_init_dt_scan_model, NULL);
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}
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void __init __dt_setup_arch(struct boot_param_header *bph)
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@ -1,9 +1,14 @@
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From e0fbc01d33265d32fe7f5f34269cb88be2a13c24 Mon Sep 17 00:00:00 2001
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From 16d9eaf22f30ed0b0deddfe8e11426889ccdb556 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 31 Mar 2013 10:17:26 +0200
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Subject: [PATCH] MIPS: ralink: handle PCI interrupts as well
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Date: Wed, 10 Apr 2013 09:07:27 +0200
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Subject: [PATCH 101/137] MIPS: ralink: add PCI IRQ handling
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The Ralink IRQ code was not handling the PCI IRQ yet. Add this functionaility
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to make PCI work on rt3883.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5165/
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---
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arch/mips/ralink/irq.c | 4 ++++
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1 file changed, 4 insertions(+)
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@ -1,34 +1,35 @@
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From 5157985fbc0f071276b0c3381ac8ed191878358a Mon Sep 17 00:00:00 2001
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From e6bcdad6f0811daedc2a448f5d7fb98c116a5241 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 19:01:49 +0100
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Subject: [PATCH 103/121] MIPS: ralink: add RT3352 usb register defines
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Subject: [PATCH 102/137] MIPS: ralink: add RT3352 register defines
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Add a few missing defines that are needed to make USB work on the RT3352
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and RT5350.
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Add a few missing defines that are needed to make USB and clock detection work
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on the RT3352.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5166/
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 11 +++++++++++
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1 file changed, 11 insertions(+)
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arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -144,4 +144,18 @@ static inline int soc_is_rt5350(void)
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@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
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#define RT305X_GPIO_MODE_SDRAM BIT(8)
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#define RT305X_GPIO_MODE_RGMII BIT(9)
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+#define RT3352_SYSC_REG_SYSCFG0 0x010
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+#define RT3352_SYSC_REG_SYSCFG1 0x014
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+#define RT3352_SYSC_REG_CLKCFG1 0x030
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+#define RT3352_SYSC_REG_RSTCTRL 0x034
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+#define RT3352_SYSC_REG_USB_PS 0x05c
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+
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+#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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+#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
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+#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
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+#define RT3352_RSTCTRL_UHST BIT(22)
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+#define RT3352_RSTCTRL_UDEV BIT(25)
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+#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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+
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+#define RT3352_SYSC_REG_SYSCFG0 0x010
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+#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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+
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#endif
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@ -1,33 +1,37 @@
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From eb8d7fbba907df0a51e504930c00b2c9ec837b54 Mon Sep 17 00:00:00 2001
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From 845f786c561c0991d9b4088a2d77b8fd4831d487 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 22 Mar 2013 19:25:59 +0100
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Subject: [PATCH 100/121] MIPS: ralink: fix RT305x clock setup
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Subject: [PATCH 103/137] MIPS: ralink: fix RT305x clock setup
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Add a few missing clocks and remove the unused sys clock.
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Add a few missing clocks.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5167/
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---
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arch/mips/ralink/rt305x.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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arch/mips/ralink/rt305x.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
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@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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+ unsigned long wmac_rate = 40000000;
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+
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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+ int wmac_20mhz = 0;
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if (soc_is_rt305x() || soc_is_rt3350()) {
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t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
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@@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
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@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
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BUG();
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}
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+ if (soc_is_rt3352() || soc_is_rt5350()) {
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+ u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
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+ if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
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+ wmac_20mhz = 1;
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+
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+ if (!(val & RT3352_CLKCFG0_XTAL_SEL))
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+ wmac_rate = 20000000;
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+ }
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+
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ralink_clk_add("cpu", cpu_rate);
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@ -37,11 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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ralink_clk_add("10000500.uart", uart_rate);
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ralink_clk_add("10000c00.uartlite", uart_rate);
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+ ralink_clk_add("10100000.ethernet", sys_rate);
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+
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+ if (wmac_20mhz)
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+ ralink_clk_add("10180000.wmac", 20000000);
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+ else
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+ ralink_clk_add("10180000.wmac", 40000000);
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+ ralink_clk_add("10180000.wmac", wmac_rate);
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}
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void __init ralink_of_remap(void)
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@ -1,18 +1,20 @@
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From 68dba842ed23c9688340444b44951c448f4ff9ba Mon Sep 17 00:00:00 2001
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From 2747613b1bba0d4497ed2c4a77e2011d02029153 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 16 Mar 2013 16:28:54 +0100
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Subject: [PATCH 101/121] MIPS: ralink: add missing comment in irq driver
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Subject: [PATCH 104/137] MIPS: ralink: add missing comment in irq driver
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Trivial patch that adds a comment that makes the code more readable.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5168/
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---
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arch/mips/ralink/irq.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/mips/ralink/irq.c
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+++ b/arch/mips/ralink/irq.c
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@@ -162,6 +162,7 @@ static int __init intc_of_init(struct de
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@@ -166,6 +166,7 @@ static int __init intc_of_init(struct de
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irq_set_chained_handler(irq, ralink_intc_irq_handler);
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irq_set_handler_data(irq, domain);
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@ -1,159 +0,0 @@
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From 45e797ec7555c50775d9ac7fc7a17a544344aa3f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 17:47:07 +0100
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Subject: [PATCH 105/121] MIPS: extend RT3050 dtsi file
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Add some additional properties to the dtsi file for ethernet and wifi.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/dts/rt3050.dtsi | 96 ++++++++++++++++++++++++++++++++------
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1 file changed, 81 insertions(+), 15 deletions(-)
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--- a/arch/mips/ralink/dts/rt3050.dtsi
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+++ b/arch/mips/ralink/dts/rt3050.dtsi
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@@ -1,7 +1,7 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
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+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
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cpus {
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cpu@0 {
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@@ -23,7 +23,7 @@
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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- ranges = <0x0 0x10000000 0x1FFFFF>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -34,8 +34,18 @@
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};
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timer@100 {
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+ compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
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+ reg = <0x100 0x20>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <1>;
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+
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+ status = "disabled";
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+ };
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+
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+ watchdog@120 {
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compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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- reg = <0x100 0x100>;
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+ reg = <0x120 0x10>;
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};
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intc: intc@200 {
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@@ -61,10 +71,12 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <24>;
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- ralink,regs = [ 00 04 08 0c
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- 20 24 28 2c
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- 30 34 ];
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+ ralink,num-gpios = <24>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+
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+ status = "disabled";
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};
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gpio1: gpio@638 {
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@@ -74,10 +86,12 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <16>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
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+ ralink,num-gpios = <16>;
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+ ralink,register-map = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+
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+ status = "disabled";
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};
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gpio2: gpio@660 {
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@@ -87,10 +101,21 @@
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gpio-controller;
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#gpio-cells = <2>;
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- ralink,ngpio = <12>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
|
||||
+ ralink,num-gpios = <12>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
uartlite@c00 {
|
||||
@@ -102,5 +127,46 @@
|
||||
|
||||
reg-shift = <2>;
|
||||
};
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt3050-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ compatible = "ralink,rt3050-esw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ wmac@10180000 {
|
||||
+ compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
|
||||
+ reg = <0x10180000 40000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ otg@101c0000 {
|
||||
+ compatible = "ralink,rt3050-otg";
|
||||
+ reg = <0x101c0000 40000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
};
|
||||
};
|
|
@ -1,12 +1,14 @@
|
|||
From ac2614707be7ddceb0f0b623d55d200f28695d5f Mon Sep 17 00:00:00 2001
|
||||
From 31f4b3ca1c9bb4bcbbebbe5db5a33ac82f130d9c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 25 Mar 2013 11:19:58 +0100
|
||||
Subject: [PATCH 102/121] MIPS: ralink: add RT5350 sdram register defines
|
||||
Subject: [PATCH 105/137] MIPS: ralink: add RT5350 sdram register defines
|
||||
|
||||
Add a few missing defines that are needed to make memory detection work on the
|
||||
RT5350.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5169/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt305x.h | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
|
@ -1,198 +0,0 @@
|
|||
From 1238d973f3828a65ccf9aead437b4e04925b100e Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:47:24 +0100
|
||||
Subject: [PATCH 106/121] MIPS: add RT5350 dtsi file
|
||||
|
||||
Add a dtsi file for RT5350 Soc. This SoC is almost the same as RT3050 but has
|
||||
OHCI/EHCI in favour of the Synopsis DWC2 core.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/dts/rt5350.dtsi | 181 ++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 181 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt5350.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt5350.dtsi
|
||||
@@ -0,0 +1,181 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt5350-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600 init=/init";
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,rt5350-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt5350-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt5350-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <12>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt5350-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt5350-eth", "ralink,rt3050-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ esw@10110000 {
|
||||
+ compatible = "ralink,rt5350-esw", "ralink,rt3050-esw";
|
||||
+ reg = <0x10110000 8000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <17>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ wmac@10180000 {
|
||||
+ compatible = "ralink,rt5350-wmac", "ralink,rt2880-wmac";
|
||||
+ reg = <0x10180000 40000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ehci@101c0000 {
|
||||
+ compatible = "ralink,rt5350-ehci", "ehci-platform";
|
||||
+ reg = <0x101c0000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ohci@101c1000 {
|
||||
+ compatible = "ralink,rt5350-ohci", "ohci-platform";
|
||||
+ reg = <0x101c1000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
|
@ -1,11 +1,13 @@
|
|||
From 3f32be8f012fb5476ea916e583e584cccc632a84 Mon Sep 17 00:00:00 2001
|
||||
From d83e83a544258b68b4411232a31ccce134244a19 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 9 Apr 2013 18:31:15 +0200
|
||||
Subject: [PATCH V2 08/16] MIPS: ralink: make early_printk work on RT2880
|
||||
Subject: [PATCH 106/137] MIPS: ralink: make early_printk work on RT2880
|
||||
|
||||
RT2880 has a different location for the early serial port.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5170/
|
||||
---
|
||||
arch/mips/ralink/early_printk.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
|
@ -0,0 +1,36 @@
|
|||
From b4c597bd073d5e4c9cee800ac5a25fb9ff1c0ef7 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 22:12:09 +0200
|
||||
Subject: [PATCH 107/137] MIPS: ralink: rename gpio_pinmux to rt_gpio_pinmux
|
||||
|
||||
Add proper namespacing to the variable.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5171/
|
||||
---
|
||||
arch/mips/ralink/common.h | 2 +-
|
||||
arch/mips/ralink/rt305x.c | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -24,7 +24,7 @@ struct ralink_pinmux {
|
||||
int uart_shift;
|
||||
void (*wdt_reset)(void);
|
||||
};
|
||||
-extern struct ralink_pinmux gpio_pinmux;
|
||||
+extern struct ralink_pinmux rt_gpio_pinmux;
|
||||
|
||||
struct ralink_soc_info {
|
||||
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -114,7 +114,7 @@ void rt305x_wdt_reset(void)
|
||||
rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
|
||||
}
|
||||
|
||||
-struct ralink_pinmux gpio_pinmux = {
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.mode = mode_mux,
|
||||
.uart = uart_mux,
|
||||
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
|
|
@ -1,210 +0,0 @@
|
|||
From b72ae753b73cbc4b488dcdbf997faec199c8bb3f Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 18:29:02 +0100
|
||||
Subject: [PATCH 108/121] MIPS: add rt2880 dts files
|
||||
|
||||
Add a dtsi file for RT2880 SoC and a sample dts file. This SoC is first one that
|
||||
was released in this SoC family.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 ++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt2880.dtsi | 116 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt2880_eval.dts | 52 +++++++++++++++
|
||||
4 files changed, 173 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -26,6 +26,10 @@ choice
|
||||
config DTB_RT_NONE
|
||||
bool "None"
|
||||
|
||||
+ config DTB_RT2880_EVAL
|
||||
+ bool "RT2880 eval kit"
|
||||
+ depends on SOC_RT288X
|
||||
+
|
||||
config DTB_RT305X_EVAL
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1 +1,2 @@
|
||||
+obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880.dtsi
|
||||
@@ -0,0 +1,116 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt2880-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600 init=/init";
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@300000 {
|
||||
+ compatible = "ralink,rt2880-sysc";
|
||||
+ reg = <0x300000 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@300100 {
|
||||
+ compatible = "ralink,rt2880-timer";
|
||||
+ reg = <0x300100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ watchdog@300120 {
|
||||
+ compatible = "ralink,rt2880-wdt";
|
||||
+ reg = <0x300120 0x10>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@300200 {
|
||||
+ compatible = "ralink,rt2880-intc";
|
||||
+ reg = <0x300200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300300 {
|
||||
+ compatible = "ralink,rt2880-memc";
|
||||
+ reg = <0x300300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@300600 {
|
||||
+ compatible = "ralink,rt2880-gpio";
|
||||
+ reg = <0x300600 0x34>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@300638 {
|
||||
+ compatible = "ralink,rt2880-gpio";
|
||||
+ reg = <0x300638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@300660 {
|
||||
+ compatible = "ralink,rt2880-gpio";
|
||||
+ reg = <0x300660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+ };
|
||||
+
|
||||
+ uartlite@300c00 {
|
||||
+ compatible = "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0x300c00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
|
||||
@@ -0,0 +1,52 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt2880.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
|
||||
+ model = "Ralink RT2880 evaluation board";
|
||||
+
|
||||
+ memory@8000000 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@300000 {
|
||||
+ ralink,pinmux = "uartlite", "spi";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cfi@1f000000 {
|
||||
+ compatible = "cfi-flash";
|
||||
+ reg = <0x1f000000 0x800000>;
|
||||
+
|
||||
+ bank-width = <2>;
|
||||
+ device-width = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@30000 {
|
||||
+ label = "uboot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@40000 {
|
||||
+ label = "calibration";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@50000 {
|
||||
+ label = "linux";
|
||||
+ reg = <0x50000 0x7b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,44 @@
|
|||
From 96eba63bf18cd3d96ded62fb809c8cf7e0f2e2c1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 22:16:12 +0200
|
||||
Subject: [PATCH 108/137] MIPS: ralink: make the RT305x pinmuxing structure
|
||||
static
|
||||
|
||||
These structures are exported via struct ralink_pinmux rt_gpio_pinmux and can
|
||||
hence be static.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5172/
|
||||
---
|
||||
arch/mips/ralink/rt305x.c | 6 +++---
|
||||
1 file changed, 3 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -22,7 +22,7 @@
|
||||
|
||||
enum rt305x_soc_type rt305x_soc;
|
||||
|
||||
-struct ralink_pinmux_grp mode_mux[] = {
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
{
|
||||
.name = "i2c",
|
||||
.mask = RT305X_GPIO_MODE_I2C,
|
||||
@@ -61,7 +61,7 @@ struct ralink_pinmux_grp mode_mux[] = {
|
||||
}, {0}
|
||||
};
|
||||
|
||||
-struct ralink_pinmux_grp uart_mux[] = {
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
{
|
||||
.name = "uartf",
|
||||
.mask = RT305X_GPIO_MODE_UARTF,
|
||||
@@ -103,7 +103,7 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
}, {0}
|
||||
};
|
||||
|
||||
-void rt305x_wdt_reset(void)
|
||||
+static void rt305x_wdt_reset(void)
|
||||
{
|
||||
u32 t;
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 61d50d9625dcb454759950ebd45a335c3aaacf84 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 12:40:23 +0200
|
||||
Subject: [PATCH 109/137] MIPS: ralink: add pci group to struct ralink_pinmux
|
||||
|
||||
This will be used for RT3662/RT3883.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Acked-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5173/
|
||||
---
|
||||
arch/mips/ralink/common.h | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -23,6 +23,9 @@ struct ralink_pinmux {
|
||||
struct ralink_pinmux_grp *uart;
|
||||
int uart_shift;
|
||||
void (*wdt_reset)(void);
|
||||
+ struct ralink_pinmux_grp *pci;
|
||||
+ int pci_shift;
|
||||
+ u32 pci_mask;
|
||||
};
|
||||
extern struct ralink_pinmux rt_gpio_pinmux;
|
||||
|
|
@ -1,282 +0,0 @@
|
|||
From 9d13fedc08f4e2cd9640983c2af8b9e9c64c094b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 18:37:00 +0100
|
||||
Subject: [PATCH 110/121] MIPS: add rt3883 dts files
|
||||
|
||||
Add a dtsi file for RT3883 SoC. This SoC is almost the same as RT3050 but has
|
||||
OHCI/EHCI in favour of the Synopsis DWC2 core. There is also a 3x3 802.11n
|
||||
wifi core.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt3883.dtsi | 186 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt3883_eval.dts | 52 ++++++++++
|
||||
4 files changed, 243 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -39,6 +39,10 @@ choice
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
|
||||
+ config DTB_RT3883_EVAL
|
||||
+ bool "RT3883 eval kit"
|
||||
+ depends on SOC_RT3883
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883.dtsi
|
||||
@@ -0,0 +1,186 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt3883-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips74Kc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600 init=/init";
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gpio3: gpio@688 {
|
||||
+ compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x688 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet@10100000 {
|
||||
+ compatible = "ralink,rt3883-eth";
|
||||
+ reg = <0x10100000 10000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <5>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ wmac@10180000 {
|
||||
+ compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
|
||||
+ reg = <0x10180000 40000>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <6>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ehci@101c0000 {
|
||||
+ compatible = "ralink,rt3883-ehci", "ehci-platform";
|
||||
+ reg = <0x101c0000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ ohci@101c1000 {
|
||||
+ compatible = "ralink,rt3883-ohci", "ohci-platform";
|
||||
+ reg = <0x101c1000 0x1000>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <18>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
|
||||
@@ -0,0 +1,52 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt3883.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
|
||||
+ model = "Ralink RT3883 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x4000000>;
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "uartlite", "spi";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cfi@1f000000 {
|
||||
+ compatible = "cfi-flash";
|
||||
+ reg = <0x1f000000 0x800000>;
|
||||
+
|
||||
+ bank-width = <2>;
|
||||
+ device-width = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@30000 {
|
||||
+ label = "uboot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@40000 {
|
||||
+ label = "calibration";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@50000 {
|
||||
+ label = "linux";
|
||||
+ reg = <0x50000 0x7b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,49 @@
|
|||
From faf5989efed503b2ee689dad82bb2d60da718d99 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 12:45:27 +0200
|
||||
Subject: [PATCH 110/137] MIPS: ralink: add uart mask to struct ralink_pinmux
|
||||
|
||||
Add a field for the uart muxing mask and set it inside the rt305x setup code.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5744/
|
||||
---
|
||||
arch/mips/ralink/common.h | 1 +
|
||||
arch/mips/ralink/rt305x.c | 5 +++--
|
||||
2 files changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -22,6 +22,7 @@ struct ralink_pinmux {
|
||||
struct ralink_pinmux_grp *mode;
|
||||
struct ralink_pinmux_grp *uart;
|
||||
int uart_shift;
|
||||
+ u32 uart_mask;
|
||||
void (*wdt_reset)(void);
|
||||
struct ralink_pinmux_grp *pci;
|
||||
int pci_shift;
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -91,12 +91,12 @@ static struct ralink_pinmux_grp uart_mux
|
||||
.name = "gpio uartf",
|
||||
.mask = RT305X_GPIO_MODE_GPIO_UARTF,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
- .gpio_last = RT305X_GPIO_14,
|
||||
+ .gpio_last = RT305X_GPIO_10,
|
||||
}, {
|
||||
.name = "gpio i2s",
|
||||
.mask = RT305X_GPIO_MODE_GPIO_I2S,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
- .gpio_last = RT305X_GPIO_14,
|
||||
+ .gpio_last = RT305X_GPIO_10,
|
||||
}, {
|
||||
.name = "gpio",
|
||||
.mask = RT305X_GPIO_MODE_GPIO,
|
||||
@@ -118,6 +118,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.mode = mode_mux,
|
||||
.uart = uart_mux,
|
||||
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
|
||||
.wdt_reset = rt305x_wdt_reset,
|
||||
};
|
||||
|
|
@ -1,21 +1,23 @@
|
|||
From c4429f19cc66951962c171dba90b8747f95a654e Mon Sep 17 00:00:00 2001
|
||||
From cccb9a7b42227a442ca42d590c838c8b6fa0eba1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 27 Jan 2013 09:17:20 +0100
|
||||
Subject: [PATCH V2 09/16] MIPS: ralink: adds support for RT2880 SoC family
|
||||
Subject: [PATCH 111/137] MIPS: ralink: adds support for RT2880 SoC family
|
||||
|
||||
Add support code for rt2880 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5176/
|
||||
---
|
||||
arch/mips/Kconfig | 2 +-
|
||||
arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
|
||||
arch/mips/ralink/Kconfig | 3 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/rt288x.c | 143 ++++++++++++++++++++++++++++
|
||||
6 files changed, 202 insertions(+), 1 deletion(-)
|
||||
arch/mips/ralink/rt288x.c | 139 ++++++++++++++++++++++++++++
|
||||
6 files changed, 198 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
create mode 100644 arch/mips/ralink/rt288x.c
|
||||
|
||||
|
@ -98,7 +100,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -8,6 +8,7 @@
|
||||
|
||||
obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
|
||||
obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
|
||||
+obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
|
@ -120,7 +122,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/rt288x.c
|
||||
@@ -0,0 +1,143 @@
|
||||
@@ -0,0 +1,139 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
|
@ -143,7 +145,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+struct ralink_pinmux_grp mode_mux[] = {
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = RT2880_GPIO_MODE_I2C,
|
||||
|
@ -182,7 +184,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+void rt288x_wdt_reset(void)
|
||||
+static void rt288x_wdt_reset(void)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
|
@ -192,15 +194,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ rt_sysc_w32(t, SYSC_REG_CLKCFG);
|
||||
+}
|
||||
+
|
||||
+struct ralink_pinmux rt_pinmux = {
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .wdt_reset = rt288x_wdt_reset,
|
||||
+};
|
||||
+
|
||||
+void ralink_usb_platform(void)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
||||
+{
|
||||
+ unsigned long cpu_rate;
|
|
@ -1,204 +0,0 @@
|
|||
From 9c83b58b49f88a48565fad6acea921a0ae222856 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:50:05 +0100
|
||||
Subject: [PATCH 112/121] MIPS: add MT7620 dts files
|
||||
|
||||
Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
|
||||
by Mediatek.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/mt7620.dtsi | 138 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/mt7620_eval.dts | 22 ++++++
|
||||
4 files changed, 165 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -46,6 +46,10 @@ choice
|
||||
bool "RT3883 eval kit"
|
||||
depends on SOC_RT3883
|
||||
|
||||
+ config DTB_MT7620_EVAL
|
||||
+ bool "MT7620 eval kit"
|
||||
+ depends on SOC_MT7620
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,3 +1,4 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620.dtsi
|
||||
@@ -0,0 +1,138 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600 init=/init";
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@100 {
|
||||
+ compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
|
||||
+ reg = <0x100 0x20>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <1>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ watchdog@120 {
|
||||
+ compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
|
||||
+ reg = <0x120 0x10>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ gpio0: gpio@600 {
|
||||
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x600 0x34>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <24>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 20 24 28 2c
|
||||
+ 30 34 ];
|
||||
+ };
|
||||
+
|
||||
+ gpio1: gpio@638 {
|
||||
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x638 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <16>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+ };
|
||||
+
|
||||
+ gpio2: gpio@660 {
|
||||
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x660 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <32>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+ };
|
||||
+
|
||||
+ gpio3: gpio@688 {
|
||||
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
|
||||
+ reg = <0x688 0x24>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+
|
||||
+ ralink,num-gpios = <1>;
|
||||
+ ralink,register-map = [ 00 04 08 0c
|
||||
+ 10 14 18 1c
|
||||
+ 20 24 ];
|
||||
+ };
|
||||
+
|
||||
+ spi@b00 {
|
||||
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
|
||||
+ reg = <0xb00 0x100>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620_eval.dts
|
||||
@@ -0,0 +1,22 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "mt7620.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
|
||||
+ model = "Ralink MT7620 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x4000000>;
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ sysc@0 {
|
||||
+ ralink,pinmux = "uartlite", "spi";
|
||||
+ ralink,uartmux = "gpio";
|
||||
+ ralink,wdtmux = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -1,20 +1,22 @@
|
|||
From 45a8644332a85e8b099df9d467a719ded741e749 Mon Sep 17 00:00:00 2001
|
||||
From 5eb4dfe5072595e0706de3364f2da45378dbaca6 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 27 Jan 2013 09:39:02 +0100
|
||||
Subject: [PATCH 109/121] MIPS: ralink: adds support for RT3883 SoC family
|
||||
Subject: [PATCH 112/137] MIPS: ralink: adds support for RT3883 SoC family
|
||||
|
||||
Add support code for rt3883 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5185/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 5 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/rt3883.c | 207 +++++++++++++++++++++++
|
||||
5 files changed, 465 insertions(+)
|
||||
arch/mips/ralink/rt3883.c | 242 +++++++++++++++++++++++++++
|
||||
5 files changed, 500 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
create mode 100644 arch/mips/ralink/rt3883.c
|
||||
|
||||
|
@ -305,7 +307,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -0,0 +1,207 @@
|
||||
@@ -0,0 +1,242 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
|
@ -328,7 +330,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+struct ralink_pinmux_grp mode_mux[] = {
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = RT3883_GPIO_MODE_I2C,
|
||||
|
@ -382,7 +384,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+struct ralink_pinmux_grp uart_mux[] = {
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
+ {
|
||||
+ .name = "uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_UARTF,
|
||||
|
@ -406,18 +408,50 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }, {
|
||||
+ .name = "pcm gpio",
|
||||
+ .mask = RT3883_GPIO_MODE_PCM_GPIO,
|
||||
+ .gpio_first = RT3883_GPIO_10,
|
||||
+ .gpio_first = RT3883_GPIO_11,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "gpio uartf",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO_UARTF,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ .gpio_last = RT3883_GPIO_10,
|
||||
+ }, {
|
||||
+ .name = "gpio i2s",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO_I2S,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
+ .gpio_last = RT3883_GPIO_10,
|
||||
+ }, {
|
||||
+ .name = "gpio",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+static struct ralink_pinmux_grp pci_mux[] = {
|
||||
+ {
|
||||
+ .name = "pci-dev",
|
||||
+ .mask = 0,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host2",
|
||||
+ .mask = 1,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host1",
|
||||
+ .mask = 2,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-fnc",
|
||||
+ .mask = 3,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-gpio",
|
||||
+ .mask = 7,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
|
@ -431,12 +465,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
|
||||
+}
|
||||
+
|
||||
+struct ralink_pinmux rt_pinmux = {
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .uart = uart_mux,
|
||||
+ .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = RT3883_GPIO_MODE_GPIO,
|
||||
+ .wdt_reset = rt3883_wdt_reset,
|
||||
+ .pci = pci_mux,
|
||||
+ .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
|
||||
+ .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
|
||||
+};
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
|
@ -1,26 +1,28 @@
|
|||
From 8831277e0167cdcf3dc3ecc5d5a67d4fd9d0ed77 Mon Sep 17 00:00:00 2001
|
||||
From a8d7045a9530d0a9e0c65c0f81852bd57ebde53c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:49:02 +0100
|
||||
Subject: [PATCH 111/121] MIPS: ralink: adds support for MT7620 SoC family
|
||||
Subject: [PATCH 113/137] MIPS: ralink: adds support for MT7620 SoC family
|
||||
|
||||
Add support code for mt7620 SOC.
|
||||
|
||||
The code detects the SoC and registers the clk / pinmux settings.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5177/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 66 +++++++++
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 76 ++++++++++
|
||||
arch/mips/ralink/Kconfig | 3 +
|
||||
arch/mips/ralink/Makefile | 1 +
|
||||
arch/mips/ralink/Platform | 5 +
|
||||
arch/mips/ralink/mt7620.c | 215 ++++++++++++++++++++++++++++
|
||||
5 files changed, 290 insertions(+)
|
||||
arch/mips/ralink/mt7620.c | 214 ++++++++++++++++++++++++++++
|
||||
5 files changed, 299 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
create mode 100644 arch/mips/ralink/mt7620.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -0,0 +1,66 @@
|
||||
@@ -0,0 +1,76 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
|
@ -58,10 +60,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+#define CHIP_REV_VER_SHIFT 8
|
||||
+#define CHIP_REV_ECO_MASK 0xf
|
||||
+
|
||||
+#define MT7620_CPLL_SW_CONFIG_SHIFT 31
|
||||
+#define MT7620_CPLL_SW_CONFIG_MASK 0x1
|
||||
+#define MT7620_CPLL_CPU_CLK_SHIFT 24
|
||||
+#define MT7620_CPLL_CPU_CLK_MASK 0x1
|
||||
+#define CPLL_SW_CONFIG_SHIFT 31
|
||||
+#define CPLL_SW_CONFIG_MASK 0x1
|
||||
+#define CPLL_CPU_CLK_SHIFT 24
|
||||
+#define CPLL_CPU_CLK_MASK 0x1
|
||||
+#define CPLL_MULT_RATIO_SHIFT 16
|
||||
+#define CPLL_MULT_RATIO 0x7
|
||||
+#define CPLL_DIV_RATIO_SHIFT 10
|
||||
+#define CPLL_DIV_RATIO 0x3
|
||||
+
|
||||
+#define SYSCFG0_DRAM_TYPE_MASK 0x3
|
||||
+#define SYSCFG0_DRAM_TYPE_SHIFT 4
|
||||
+#define SYSCFG0_DRAM_TYPE_SDRAM 0
|
||||
+#define SYSCFG0_DRAM_TYPE_DDR1 1
|
||||
+#define SYSCFG0_DRAM_TYPE_DDR2 2
|
||||
+
|
||||
+#define MT7620_GPIO_MODE_I2C BIT(0)
|
||||
+#define MT7620_GPIO_MODE_UART0_SHIFT 2
|
||||
|
@ -122,7 +134,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -0,0 +1,215 @@
|
||||
@@ -0,0 +1,214 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
|
@ -145,8 +157,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+/* does the board have sdram or ddram */
|
||||
+static int dram_type;
|
||||
+
|
||||
+struct ralink_pinmux_grp mode_mux[] = {
|
||||
+/* the pll dividers */
|
||||
+static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
|
||||
+
|
||||
+static struct ralink_pinmux_grp mode_mux[] = {
|
||||
+ {
|
||||
+ .name = "i2c",
|
||||
+ .mask = MT7620_GPIO_MODE_I2C,
|
||||
|
@ -211,8 +228,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
+
|
||||
+struct ralink_pinmux_grp uart_mux[] = {
|
||||
+static struct ralink_pinmux_grp uart_mux[] = {
|
||||
+ {
|
||||
+ .name = "uartf",
|
||||
+ .mask = MT7620_GPIO_MODE_UARTF,
|
||||
|
@ -253,22 +269,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ .mask = MT7620_GPIO_MODE_GPIO,
|
||||
+ }, {0}
|
||||
+};
|
||||
+/*
|
||||
+void rt305x_wdt_reset(void)
|
||||
+{
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
|
||||
+ t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
|
||||
+ RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
|
||||
+ rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
|
||||
+}
|
||||
+*/
|
||||
+struct ralink_pinmux rt_pinmux = {
|
||||
+struct ralink_pinmux rt_gpio_pinmux = {
|
||||
+ .mode = mode_mux,
|
||||
+ .uart = uart_mux,
|
||||
+ .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
|
||||
+// .wdt_reset = rt305x_wdt_reset,
|
||||
+ .uart_mask = MT7620_GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+void __init ralink_clk_init(void)
|
||||
|
@ -276,23 +282,24 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ unsigned long cpu_rate, sys_rate;
|
||||
+ u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
|
||||
+ u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
|
||||
+ u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
|
||||
+ u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
|
||||
+
|
||||
+ c0 = (c0 >> MT7620_CPLL_SW_CONFIG_SHIFT) &
|
||||
+ MT7620_CPLL_SW_CONFIG_MASK;
|
||||
+ c1 = (c1 >> MT7620_CPLL_CPU_CLK_SHIFT) &
|
||||
+ MT7620_CPLL_CPU_CLK_MASK;
|
||||
+ if (c1 == 0x01) {
|
||||
+ if (cpu_clk) {
|
||||
+ cpu_rate = 480000000;
|
||||
+ } else if (!swconfig) {
|
||||
+ cpu_rate = 600000000;
|
||||
+ } else {
|
||||
+ if (c1 == 0x0) {
|
||||
+ cpu_rate = 600000000;
|
||||
+ } else {
|
||||
+ /* TODO calculate custom clock from pll settings */
|
||||
+ BUG();
|
||||
+ }
|
||||
+ u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
|
||||
+ u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
|
||||
+
|
||||
+ cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
|
||||
+ }
|
||||
+ /* FIXME SDR - 4, DDR - 3 */
|
||||
+ sys_rate = cpu_rate / 4;
|
||||
+
|
||||
+ if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
|
||||
+ sys_rate = cpu_rate / 4;
|
||||
+ else
|
||||
+ sys_rate = cpu_rate / 3;
|
||||
+
|
||||
+ ralink_clk_add("cpu", cpu_rate);
|
||||
+ ralink_clk_add("10000100.timer", 40000000);
|
||||
|
@ -302,8 +309,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+void __init ralink_of_remap(void)
|
||||
+{
|
||||
+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620-sysc");
|
||||
+ rt_memc_membase = plat_of_remap_node("ralink,mt7620-memc");
|
||||
+ rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
|
||||
+ rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
|
||||
+
|
||||
+ if (!rt_sysc_membase || !rt_memc_membase)
|
||||
+ panic("Failed to remap core resources");
|
||||
|
@ -316,6 +323,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ u32 n0;
|
||||
+ u32 n1;
|
||||
+ u32 rev;
|
||||
+ u32 cfg0;
|
||||
+
|
||||
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||||
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||||
|
@ -327,7 +335,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ name = "MT7620A";
|
||||
+ soc_info->compatible = "ralink,mt7620a-soc";
|
||||
+ } else {
|
||||
+ printk("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
|
||||
+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
|
||||
+ }
|
||||
+
|
||||
+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
|
||||
|
@ -337,4 +345,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ name,
|
||||
+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
|
||||
+ (rev & CHIP_REV_ECO_MASK));
|
||||
+
|
||||
+ cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
|
||||
+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
|
||||
+}
|
|
@ -0,0 +1,218 @@
|
|||
From 33c525913af22d1b799a7218ee48579c22a50cf8 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 10 Apr 2013 09:19:07 +0200
|
||||
Subject: [PATCH 114/137] MIPS: ralink: add cpu-feature-overrides.h
|
||||
|
||||
Add cpu-feature-overrides.h for RT288x, RT305x and RT3883.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5175/
|
||||
---
|
||||
.../asm/mach-ralink/rt288x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
.../asm/mach-ralink/rt305x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
.../asm/mach-ralink/rt3883/cpu-feature-overrides.h | 55 +++++++++++++++++++
|
||||
arch/mips/ralink/Platform | 3 ++
|
||||
4 files changed, 170 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT288x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 0
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 16
|
||||
+#define cpu_icache_line_size() 16
|
||||
+
|
||||
+#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT305x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -8,16 +8,19 @@ cflags-$(CONFIG_RALINK) += -I$(srctree)
|
||||
# Ralink RT288x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
|
||||
+cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
|
||||
|
||||
#
|
||||
# Ralink RT305x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
|
||||
|
||||
#
|
||||
# Ralink RT3883
|
||||
#
|
||||
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
|
||||
|
||||
#
|
||||
# Ralink MT7620
|
|
@ -0,0 +1,21 @@
|
|||
From 9377ecb9f1fb5da25a0fbd324e7add7644b1d43d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 10:11:51 +0200
|
||||
Subject: [PATCH 115/137] DT: add vendor prefixes for Ralink
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
---
|
||||
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
|
||||
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
|
||||
@@ -40,6 +40,7 @@ onnn ON Semiconductor Corp.
|
||||
picochip Picochip Ltd
|
||||
powervr PowerVR (deprecated, use img)
|
||||
qcom Qualcomm, Inc.
|
||||
+ralink Mediatek/Ralink Technology Corp.
|
||||
ramtron Ramtron International
|
||||
realtek Realtek Semiconductor Corp.
|
||||
samsung Samsung Semiconductor
|
|
@ -0,0 +1,38 @@
|
|||
From fed1ff0d85b481bb3dbebf31e0720d65ce4170c9 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 09:02:40 +0200
|
||||
Subject: [PATCH 116/137] DT: add documentation for the Ralink MIPS SoCs
|
||||
|
||||
This patch adds binding documentation for the
|
||||
compatible values of the Ralink MIPS SoCs.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5187/
|
||||
---
|
||||
Documentation/devicetree/bindings/mips/ralink.txt | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/mips/ralink.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
|
||||
@@ -0,0 +1,18 @@
|
||||
+Ralink MIPS SoC device tree bindings
|
||||
+
|
||||
+1. SoCs
|
||||
+
|
||||
+Each device tree must specify a compatible value for the Ralink SoC
|
||||
+it uses in the compatible property of the root node. The compatible
|
||||
+value must be one of the following values:
|
||||
+
|
||||
+ ralink,rt2880-soc
|
||||
+ ralink,rt3050-soc
|
||||
+ ralink,rt3052-soc
|
||||
+ ralink,rt3350-soc
|
||||
+ ralink,rt3352-soc
|
||||
+ ralink,rt3883-soc
|
||||
+ ralink,rt5350-soc
|
||||
+ ralink,mt7620a-soc
|
||||
+ ralink,mt7620n-soc
|
||||
+
|
|
@ -0,0 +1,117 @@
|
|||
From 7a30e00a278fe94ac8e42d0967ffde99d1ab74ee Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:47:07 +0100
|
||||
Subject: [PATCH 117/137] DT: MIPS: ralink: clean up RT3050 dtsi and dts file
|
||||
|
||||
* remove nodes for cores whose drivers are not upstream yet
|
||||
* add compat string for an additional soc
|
||||
* fix a whitespace error
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5186/
|
||||
---
|
||||
arch/mips/ralink/dts/rt3050.dtsi | 52 ++--------------------------------
|
||||
arch/mips/ralink/dts/rt3052_eval.dts | 10 ++-----
|
||||
2 files changed, 4 insertions(+), 58 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/dts/rt3050.dtsi
|
||||
+++ b/arch/mips/ralink/dts/rt3050.dtsi
|
||||
@@ -1,7 +1,7 @@
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
|
||||
+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
@@ -9,10 +9,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- chosen {
|
||||
- bootargs = "console=ttyS0,57600 init=/init";
|
||||
- };
|
||||
-
|
||||
cpuintc: cpuintc@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
@@ -23,7 +19,7 @@
|
||||
palmbus@10000000 {
|
||||
compatible = "palmbus";
|
||||
reg = <0x10000000 0x200000>;
|
||||
- ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -33,11 +29,6 @@
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
- timer@100 {
|
||||
- compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
|
||||
- reg = <0x100 0x100>;
|
||||
- };
|
||||
-
|
||||
intc: intc@200 {
|
||||
compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
|
||||
reg = <0x200 0x100>;
|
||||
@@ -54,45 +45,6 @@
|
||||
reg = <0x300 0x100>;
|
||||
};
|
||||
|
||||
- gpio0: gpio@600 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x600 0x34>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <24>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 20 24 28 2c
|
||||
- 30 34 ];
|
||||
- };
|
||||
-
|
||||
- gpio1: gpio@638 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x638 0x24>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <16>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 10 14 18 1c
|
||||
- 20 24 ];
|
||||
- };
|
||||
-
|
||||
- gpio2: gpio@660 {
|
||||
- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
|
||||
- reg = <0x660 0x24>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
-
|
||||
- ralink,ngpio = <12>;
|
||||
- ralink,regs = [ 00 04 08 0c
|
||||
- 10 14 18 1c
|
||||
- 20 24 ];
|
||||
- };
|
||||
-
|
||||
uartlite@c00 {
|
||||
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
--- a/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
|
||||
@@ -3,8 +3,6 @@
|
||||
/include/ "rt3050.dtsi"
|
||||
|
||||
/ {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
|
||||
model = "Ralink RT3052 evaluation board";
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
From b39e659770cb71939765de8c9e73c0a0cfa832db Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:37 +0000
|
||||
Subject: [PATCH 118/137] DT: MIPS: ralink: add RT2880 dts files
|
||||
|
||||
Add a dtsi file for RT2880 SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5188/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt2880.dtsi | 58 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt2880_eval.dts | 46 +++++++++++++++++++++++++++
|
||||
4 files changed, 109 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -34,6 +34,10 @@ choice
|
||||
config DTB_RT_NONE
|
||||
bool "None"
|
||||
|
||||
+ config DTB_RT2880_EVAL
|
||||
+ bool "RT2880 eval kit"
|
||||
+ depends on SOC_RT288X
|
||||
+
|
||||
config DTB_RT305X_EVAL
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1 +1,2 @@
|
||||
+obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt2880-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips4KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@300000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x300000 0x200000>;
|
||||
+ ranges = <0x0 0x300000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt2880-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt2880-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <8>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
|
||||
@@ -0,0 +1,46 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt2880.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
|
||||
+ model = "Ralink RT2880 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x8000000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+
|
||||
+ cfi@1f000000 {
|
||||
+ compatible = "cfi-flash";
|
||||
+ reg = <0x1f000000 0x400000>;
|
||||
+
|
||||
+ bank-width = <2>;
|
||||
+ device-width = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0x0 0x30000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@30000 {
|
||||
+ label = "uboot-env";
|
||||
+ reg = <0x30000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@40000 {
|
||||
+ label = "calibration";
|
||||
+ reg = <0x40000 0x10000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+ partition@50000 {
|
||||
+ label = "linux";
|
||||
+ reg = <0x50000 0x3b0000>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,118 @@
|
|||
From 8b02459b5aa171dc8726698c4b19341a4e441bb8 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:39 +0000
|
||||
Subject: [PATCH 119/137] DT: MIPS: ralink: add RT3883 dts files
|
||||
|
||||
Add a dtsi file for RT3883 SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5189/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/rt3883.dtsi | 58 ++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/rt3883_eval.dts | 16 ++++++++++
|
||||
4 files changed, 79 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/rt3883_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -42,6 +42,10 @@ choice
|
||||
bool "RT305x eval kit"
|
||||
depends on SOC_RT305X
|
||||
|
||||
+ config DTB_RT3883_EVAL
|
||||
+ bool "RT3883 eval kit"
|
||||
+ depends on SOC_RT3883
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,2 +1,3 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,rt3883-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips74Kc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "rt3883.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
|
||||
+ model = "Ralink RT3883 evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+};
|
|
@ -1,525 +0,0 @@
|
|||
From f01830fcc57273bd9ec5f6733ab3d28adeb71955 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:34:08 +0100
|
||||
Subject: [PATCH 119/121] PCI: MIPS: adds rt3883 pci support
|
||||
|
||||
Add support for the pcie found on the rt3883 SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/pci/Makefile | 1 +
|
||||
arch/mips/pci/pci-rt3883.c | 487 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
3 files changed, 489 insertions(+)
|
||||
create mode 100644 arch/mips/pci/pci-rt3883.c
|
||||
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
|
||||
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
|
||||
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
|
||||
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
|
||||
+obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
|
||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/pci/pci-rt3883.c
|
||||
@@ -0,0 +1,487 @@
|
||||
+/*
|
||||
+ * Ralink RT3883 SoC PCI support
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/rt3883.h>
|
||||
+#include <asm/mach-ralink/rt3883_regs.h>
|
||||
+
|
||||
+#define RT3883_MEMORY_BASE 0x00000000
|
||||
+#define RT3883_MEMORY_SIZE 0x02000000
|
||||
+
|
||||
+#define RT3883_PCI_MEM_BASE 0x20000000
|
||||
+#define RT3883_PCI_MEM_SIZE 0x10000000
|
||||
+#define RT3883_PCI_IO_BASE 0x10160000
|
||||
+#define RT3883_PCI_IO_SIZE 0x00010000
|
||||
+
|
||||
+#define RT3883_PCI_REG_PCICFG_ADDR 0x00
|
||||
+#define RT3883_PCI_REG_PCIRAW_ADDR 0x04
|
||||
+#define RT3883_PCI_REG_PCIINT_ADDR 0x08
|
||||
+#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
|
||||
+#define RT3833_PCI_PCIINT_PCIE BIT(20)
|
||||
+#define RT3833_PCI_PCIINT_PCI1 BIT(19)
|
||||
+#define RT3833_PCI_PCIINT_PCI0 BIT(18)
|
||||
+
|
||||
+#define RT3883_PCI_REG_CONFIG_ADDR 0x20
|
||||
+#define RT3883_PCI_REG_CONFIG_DATA 0x24
|
||||
+#define RT3883_PCI_REG_MEMBASE 0x28
|
||||
+#define RT3883_PCI_REG_IOBASE 0x2c
|
||||
+#define RT3883_PCI_REG_ARBCTL 0x80
|
||||
+
|
||||
+#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
|
||||
+#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
|
||||
+#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
|
||||
+#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
|
||||
+#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
|
||||
+#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
|
||||
+#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
|
||||
+
|
||||
+static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
+static void __iomem *rt3883_pci_base;
|
||||
+static DEFINE_SPINLOCK(rt3883_pci_lock);
|
||||
+
|
||||
+static inline u32 rt3883_pci_rr(unsigned reg)
|
||||
+{
|
||||
+ return readl(rt3883_pci_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void rt3883_pci_wr(u32 val, unsigned reg)
|
||||
+{
|
||||
+ writel(val, rt3883_pci_base + reg);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
+ unsigned int func, unsigned int where)
|
||||
+{
|
||||
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
|
||||
+ 0x80000000);
|
||||
+}
|
||||
+
|
||||
+static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
|
||||
+ unsigned func, unsigned reg)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 ret;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
+ rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
+ ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
|
||||
+ unsigned func, unsigned reg, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
+ rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
+ rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 pending;
|
||||
+
|
||||
+ pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
|
||||
+ rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ if (!pending) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (pending & RT3833_PCI_PCIINT_PCI0)
|
||||
+ generic_handle_irq(RT3883_PCI_IRQ_PCI0);
|
||||
+
|
||||
+ if (pending & RT3833_PCI_PCIINT_PCI1)
|
||||
+ generic_handle_irq(RT3883_PCI_IRQ_PCI1);
|
||||
+
|
||||
+ if (pending & RT3833_PCI_PCIINT_PCIE)
|
||||
+ generic_handle_irq(RT3883_PCI_IRQ_PCIE);
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ int irq = d->irq;
|
||||
+ u32 mask;
|
||||
+ u32 t;
|
||||
+
|
||||
+ switch (irq) {
|
||||
+ case RT3883_PCI_IRQ_PCI0:
|
||||
+ mask = RT3833_PCI_PCIINT_PCI0;
|
||||
+ break;
|
||||
+ case RT3883_PCI_IRQ_PCI1:
|
||||
+ mask = RT3833_PCI_PCIINT_PCI1;
|
||||
+ break;
|
||||
+ case RT3883_PCI_IRQ_PCIE:
|
||||
+ mask = RT3833_PCI_PCIINT_PCIE;
|
||||
+ break;
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+
|
||||
+ t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ int irq = d->irq;
|
||||
+ u32 mask;
|
||||
+ u32 t;
|
||||
+
|
||||
+ switch (irq) {
|
||||
+ case RT3883_PCI_IRQ_PCI0:
|
||||
+ mask = RT3833_PCI_PCIINT_PCI0;
|
||||
+ break;
|
||||
+ case RT3883_PCI_IRQ_PCI1:
|
||||
+ mask = RT3833_PCI_PCIINT_PCI1;
|
||||
+ break;
|
||||
+ case RT3883_PCI_IRQ_PCIE:
|
||||
+ mask = RT3833_PCI_PCIINT_PCIE;
|
||||
+ break;
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+
|
||||
+ t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip rt3883_pci_irq_chip = {
|
||||
+ .name = "RT3883 PCI",
|
||||
+ .irq_mask = rt3883_pci_irq_mask,
|
||||
+ .irq_unmask = rt3883_pci_irq_unmask,
|
||||
+ .irq_mask_ack = rt3883_pci_irq_mask,
|
||||
+};
|
||||
+
|
||||
+static void __init rt3883_pci_irq_init(void)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ /* disable all interrupts */
|
||||
+ rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ for (i = RT3883_PCI_IRQ_BASE;
|
||||
+ i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
|
||||
+ irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
|
||||
+ handle_level_irq);
|
||||
+ }
|
||||
+
|
||||
+ irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
+ rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
+ data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ *val = data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
+ rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
+ data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ data = val;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
|
||||
+ spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops rt3883_pci_ops = {
|
||||
+ .read = rt3883_pci_config_read,
|
||||
+ .write = rt3883_pci_config_write,
|
||||
+};
|
||||
+
|
||||
+static struct resource rt3883_pci_mem_resource = {
|
||||
+ .name = "PCI MEM space",
|
||||
+ .start = RT3883_PCI_MEM_BASE,
|
||||
+ .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+};
|
||||
+
|
||||
+static struct resource rt3883_pci_io_resource = {
|
||||
+ .name = "PCI IO space",
|
||||
+ .start = RT3883_PCI_IO_BASE,
|
||||
+ .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
|
||||
+ .flags = IORESOURCE_IO,
|
||||
+};
|
||||
+
|
||||
+static struct pci_controller rt3883_pci_controller = {
|
||||
+ .pci_ops = &rt3883_pci_ops,
|
||||
+ .mem_resource = &rt3883_pci_mem_resource,
|
||||
+ .io_resource = &rt3883_pci_io_resource,
|
||||
+};
|
||||
+
|
||||
+static void rt3883_pci_preinit(unsigned mode)
|
||||
+{
|
||||
+ u32 syscfg1;
|
||||
+ u32 rstctrl;
|
||||
+ u32 clkcfg1;
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
|
||||
+ val &= ~(0x30);
|
||||
+ val |= (2 << 4);
|
||||
+ rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
|
||||
+
|
||||
+ val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ val &= ~BIT(31);
|
||||
+ rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+
|
||||
+ val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+ val &= 0x80ffffff;
|
||||
+ rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+
|
||||
+ val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+ val |= 0xa << 24;
|
||||
+ rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
+
|
||||
+ val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ val |= BIT(31);
|
||||
+ rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+
|
||||
+ msleep(50);
|
||||
+ }
|
||||
+
|
||||
+ syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
|
||||
+ syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
|
||||
+ RT3883_SYSCFG1_PCI_HOST_MODE);
|
||||
+
|
||||
+ rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
|
||||
+ rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
|
||||
+
|
||||
+ clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
|
||||
+ clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
|
||||
+ RT3883_CLKCFG1_PCIE_CLK_EN);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCI) {
|
||||
+ syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCI;
|
||||
+ }
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
|
||||
+ RT3883_SYSCFG1_PCIE_RC_MODE;
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ }
|
||||
+
|
||||
+ rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
+ rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
+ rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
|
||||
+
|
||||
+ msleep(500);
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pcie_ready(void)
|
||||
+{
|
||||
+ u32 status;
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
|
||||
+ if (status & BIT(0))
|
||||
+ return 0;
|
||||
+
|
||||
+ /* TODO: reset PCIe and turn off PCIe clock */
|
||||
+
|
||||
+ return -ENODEV;
|
||||
+}
|
||||
+
|
||||
+void __init rt3883_pci_init(unsigned mode)
|
||||
+{
|
||||
+ u32 val;
|
||||
+ int err;
|
||||
+
|
||||
+ rt3883_pci_preinit(mode);
|
||||
+
|
||||
+ rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
|
||||
+ if (rt3883_pci_base == NULL) {
|
||||
+ pr_err("failed to ioremap PCI registers\n");
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
|
||||
+ if (mode & RT3883_PCI_MODE_PCI)
|
||||
+ rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ err = rt3883_pcie_ready();
|
||||
+ if (err)
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCI)
|
||||
+ rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
|
||||
+
|
||||
+ rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
|
||||
+ rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
|
||||
+
|
||||
+ /* PCI */
|
||||
+ rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
|
||||
+ rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
|
||||
+ rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
|
||||
+ rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
|
||||
+ rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
|
||||
+ rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
|
||||
+ rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
|
||||
+ rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
|
||||
+ rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
|
||||
+
|
||||
+ rt3883_pci_irq_init();
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
|
||||
+ val |= 0x7;
|
||||
+ rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ /* PCI */
|
||||
+ val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
|
||||
+ val |= 0x7;
|
||||
+ rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ ioport_resource.start = rt3883_pci_io_resource.start;
|
||||
+ ioport_resource.end = rt3883_pci_io_resource.end;
|
||||
+
|
||||
+ register_pci_controller(&rt3883_pci_controller);
|
||||
+}
|
||||
+
|
||||
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ int irq = -1;
|
||||
+
|
||||
+ switch (dev->bus->number) {
|
||||
+ case 0:
|
||||
+ switch (PCI_SLOT(dev->devfn)) {
|
||||
+ case 0x00:
|
||||
+ rt3883_pci_wr(0x03ff0001,
|
||||
+ RT3883_PCI_REG_BAR0SETUP_ADDR(0));
|
||||
+ rt3883_pci_wr(0x03ff0001,
|
||||
+ RT3883_PCI_REG_BAR0SETUP_ADDR(1));
|
||||
+
|
||||
+ rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
|
||||
+ RT3883_MEMORY_BASE);
|
||||
+ rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
|
||||
+
|
||||
+ irq = RT3883_CPU_IRQ_PCI;
|
||||
+ break;
|
||||
+ case 0x01:
|
||||
+ rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
|
||||
+ 0x00000101);
|
||||
+ break;
|
||||
+ case 0x11:
|
||||
+ irq = RT3883_PCI_IRQ_PCI0;
|
||||
+ break;
|
||||
+ case 0x12:
|
||||
+ irq = RT3883_PCI_IRQ_PCI1;
|
||||
+ break;
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case 1:
|
||||
+ irq = RT3883_PCI_IRQ_PCIE;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(&dev->dev, "no IRQ specified\n");
|
||||
+ return irq;
|
||||
+ }
|
||||
+
|
||||
+ return irq;
|
||||
+}
|
||||
+
|
||||
+void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
|
||||
+{
|
||||
+ rt3883_pci_plat_dev_init = f;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ if (rt3883_pci_plat_dev_init)
|
||||
+ return rt3883_pci_plat_dev_init(dev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -20,6 +20,7 @@ choice
|
||||
bool "RT3883"
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
+ select HW_HAS_PCI
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
|
@ -0,0 +1,119 @@
|
|||
From 07741f61fc94fad3c3d21fa1a2ad6f01455cc1dd Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 12 Apr 2013 06:27:41 +0000
|
||||
Subject: [PATCH 120/137] DT: MIPS: ralink: add MT7620A dts files
|
||||
|
||||
Add a dtsi file for MT7620A SoC and a sample dts file.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5190/
|
||||
---
|
||||
arch/mips/ralink/Kconfig | 4 +++
|
||||
arch/mips/ralink/dts/Makefile | 1 +
|
||||
arch/mips/ralink/dts/mt7620a.dtsi | 58 +++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/dts/mt7620a_eval.dts | 16 +++++++++
|
||||
4 files changed, 79 insertions(+)
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620a.dtsi
|
||||
create mode 100644 arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -46,6 +46,10 @@ choice
|
||||
bool "RT3883 eval kit"
|
||||
depends on SOC_RT3883
|
||||
|
||||
+ config DTB_MT7620A_EVAL
|
||||
+ bool "MT7620A eval kit"
|
||||
+ depends on SOC_MT7620
|
||||
+
|
||||
endchoice
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ralink/dts/Makefile
|
||||
+++ b/arch/mips/ralink/dts/Makefile
|
||||
@@ -1,3 +1,4 @@
|
||||
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
|
||||
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
|
||||
+obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
|
||||
@@ -0,0 +1,58 @@
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ compatible = "ralink,mtk7620a-soc";
|
||||
+
|
||||
+ cpus {
|
||||
+ cpu@0 {
|
||||
+ compatible = "mips,mips24KEc";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpuintc: cpuintc@0 {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ compatible = "mti,cpu-interrupt-controller";
|
||||
+ };
|
||||
+
|
||||
+ palmbus@10000000 {
|
||||
+ compatible = "palmbus";
|
||||
+ reg = <0x10000000 0x200000>;
|
||||
+ ranges = <0x0 0x10000000 0x1FFFFF>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ sysc@0 {
|
||||
+ compatible = "ralink,mt7620a-sysc";
|
||||
+ reg = <0x0 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ intc: intc@200 {
|
||||
+ compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
|
||||
+ reg = <0x200 0x100>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+ };
|
||||
+
|
||||
+ memc@300 {
|
||||
+ compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
|
||||
+ reg = <0x300 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ uartlite@c00 {
|
||||
+ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
|
||||
+ reg = <0xc00 0x100>;
|
||||
+
|
||||
+ interrupt-parent = <&intc>;
|
||||
+ interrupts = <12>;
|
||||
+
|
||||
+ reg-shift = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/dts/mt7620a_eval.dts
|
||||
@@ -0,0 +1,16 @@
|
||||
+/dts-v1/;
|
||||
+
|
||||
+/include/ "mt7620a.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
|
||||
+ model = "Ralink MT7620A evaluation board";
|
||||
+
|
||||
+ memory@0 {
|
||||
+ reg = <0x0 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,57600";
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,61 @@
|
|||
From 9041c96ab5bd29d85ca95cffa44c755f68ae6bb1 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 13:15:47 +0200
|
||||
Subject: [PATCH 121/137] MIPS: add detect_memory_region()
|
||||
|
||||
Add a generic way of detecting the available RAM. This function is based on the
|
||||
implementation already used by ath79.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5178/
|
||||
---
|
||||
arch/mips/include/asm/bootinfo.h | 1 +
|
||||
arch/mips/kernel/setup.c | 20 ++++++++++++++++++++
|
||||
2 files changed, 21 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/bootinfo.h
|
||||
+++ b/arch/mips/include/asm/bootinfo.h
|
||||
@@ -104,6 +104,7 @@ struct boot_mem_map {
|
||||
extern struct boot_mem_map boot_mem_map;
|
||||
|
||||
extern void add_memory_region(phys_t start, phys_t size, long type);
|
||||
+extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max);
|
||||
|
||||
extern void prom_init(void);
|
||||
extern void prom_free_prom_memory(void);
|
||||
--- a/arch/mips/kernel/setup.c
|
||||
+++ b/arch/mips/kernel/setup.c
|
||||
@@ -23,6 +23,7 @@
|
||||
#include <linux/pfn.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/kexec.h>
|
||||
+#include <linux/sizes.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
@@ -122,6 +123,25 @@ void __init add_memory_region(phys_t sta
|
||||
boot_mem_map.nr_map++;
|
||||
}
|
||||
|
||||
+void __init detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max)
|
||||
+{
|
||||
+ phys_t size;
|
||||
+
|
||||
+ for (size = sz_min; size < sz_max; size <<= 1) {
|
||||
+ if (!memcmp(detect_memory_region,
|
||||
+ detect_memory_region + size, 1024))
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
|
||||
+ ((unsigned long long) size) / SZ_1M,
|
||||
+ (unsigned long long) start,
|
||||
+ ((unsigned long long) sz_min) / SZ_1M,
|
||||
+ ((unsigned long long) sz_max) / SZ_1M);
|
||||
+
|
||||
+ add_memory_region(start, size, BOOT_MEM_RAM);
|
||||
+}
|
||||
+
|
||||
static void __init print_memory_map(void)
|
||||
{
|
||||
int i;
|
|
@ -0,0 +1,29 @@
|
|||
From 5155790ed1f270379ea98325f01e1c72a36a37d0 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:10:14 +0200
|
||||
Subject: [PATCH 122/137] MIPS: ralink: add memory definition to struct
|
||||
ralink_soc_info
|
||||
|
||||
Depending on the actual SoC we have a different base address as well as minimum
|
||||
and maximum size for RAM. Add these fields to the per SoC structure.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5179/
|
||||
---
|
||||
arch/mips/ralink/common.h | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -33,6 +33,11 @@ extern struct ralink_pinmux rt_gpio_pinm
|
||||
struct ralink_soc_info {
|
||||
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
|
||||
unsigned char *compatible;
|
||||
+
|
||||
+ unsigned long mem_base;
|
||||
+ unsigned long mem_size;
|
||||
+ unsigned long mem_size_min;
|
||||
+ unsigned long mem_size_max;
|
||||
};
|
||||
extern struct ralink_soc_info soc_info;
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
From 016f1f659cf70cc78e72e12a2130d8f3e1a6e0d3 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:13:40 +0200
|
||||
Subject: [PATCH 123/137] MIPS: ralink: add memory definition for RT305x
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
As memory detection fails on RT5350 we read the amount of available memory
|
||||
from the system controller.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5180/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt305x.h | 6 ++++
|
||||
arch/mips/ralink/rt305x.c | 45 ++++++++++++++++++++++++++++
|
||||
2 files changed, 51 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
|
||||
@@ -157,4 +157,10 @@ static inline int soc_is_rt5350(void)
|
||||
#define RT3352_RSTCTRL_UDEV BIT(25)
|
||||
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
|
||||
|
||||
+#define RT305X_SDRAM_BASE 0x00000000
|
||||
+#define RT305X_MEM_SIZE_MIN 2
|
||||
+#define RT305X_MEM_SIZE_MAX 64
|
||||
+#define RT3352_MEM_SIZE_MIN 2
|
||||
+#define RT3352_MEM_SIZE_MAX 256
|
||||
+
|
||||
#endif
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -122,6 +122,40 @@ struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.wdt_reset = rt305x_wdt_reset,
|
||||
};
|
||||
|
||||
+static unsigned long rt5350_get_mem_size(void)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
|
||||
+ unsigned long ret;
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
|
||||
+ t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
|
||||
+ RT5350_SYSCFG0_DRAM_SIZE_MASK;
|
||||
+
|
||||
+ switch (t) {
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_2M:
|
||||
+ ret = 2;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_8M:
|
||||
+ ret = 8;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_16M:
|
||||
+ ret = 16;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_32M:
|
||||
+ ret = 32;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_64M:
|
||||
+ ret = 64;
|
||||
+ break;
|
||||
+ default:
|
||||
+ panic("rt5350: invalid DRAM size: %u", t);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
void __init ralink_clk_init(void)
|
||||
{
|
||||
unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
|
||||
@@ -252,4 +286,15 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
|
||||
(id & CHIP_ID_REV_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT305X_SDRAM_BASE;
|
||||
+ if (soc_is_rt5350()) {
|
||||
+ soc_info->mem_size = rt5350_get_mem_size();
|
||||
+ } else if (soc_is_rt305x() || soc_is_rt3350()) {
|
||||
+ soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
|
||||
+ } else if (soc_is_rt3352()) {
|
||||
+ soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
|
||||
+ }
|
||||
}
|
|
@ -1,40 +0,0 @@
|
|||
From 34a9a634432a95d8ae9af86d41fdaf32fb039c2c Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 27 Mar 2013 21:10:14 +0100
|
||||
Subject: [PATCH 1/5] MIPS: ralink: fix uartmux group handling
|
||||
|
||||
* don't try get 'ralink,uartmux' porperty if the pinmux.uart is
|
||||
not initialized,
|
||||
* don't touch 'mode' value if mux mask is zero
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/pinmux.c | 12 ++++++++----
|
||||
1 file changed, 8 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/mips/ralink/pinmux.c
|
||||
+++ b/arch/mips/ralink/pinmux.c
|
||||
@@ -56,15 +56,19 @@ void ralink_pinmux(void)
|
||||
}
|
||||
}
|
||||
|
||||
- of_property_read_string(np, "ralink,uartmux", &uart);
|
||||
+ uart = NULL;
|
||||
+ if (rt_pinmux.uart)
|
||||
+ of_property_read_string(np, "ralink,uartmux", &uart);
|
||||
+
|
||||
if (uart) {
|
||||
int m = ralink_mux_mask(uart, rt_pinmux.uart);
|
||||
- mode |= rt_pinmux.uart_mask << rt_pinmux.uart_shift;
|
||||
+
|
||||
if (m) {
|
||||
- mode &= ~(m << rt_pinmux.uart_shift);
|
||||
+ mode &= ~(rt_pinmux.uart_mask << rt_pinmux.uart_shift);
|
||||
+ mode |= m << rt_pinmux.uart_shift;
|
||||
pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
|
||||
} else {
|
||||
- pr_debug("pinmux: registered uartmux \"gpio\"\n");
|
||||
+ pr_debug("pinmux: unknown uartmux \"%s\"\n", uart);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
From 0151f5f0dbf43b6b3718b0d1d403c87429ac0313 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:37:37 +0200
|
||||
Subject: [PATCH 124/137] MIPS: ralink: add memory definition for RT2880
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5181/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt288x.h | 4 ++++
|
||||
arch/mips/ralink/rt288x.c | 4 ++++
|
||||
2 files changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
|
||||
@@ -46,4 +46,8 @@
|
||||
|
||||
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
|
||||
|
||||
+#define RT2880_SDRAM_BASE 0x08000000
|
||||
+#define RT2880_MEM_SIZE_MIN 2
|
||||
+#define RT2880_MEM_SIZE_MAX 128
|
||||
+
|
||||
#endif
|
||||
--- a/arch/mips/ralink/rt288x.c
|
||||
+++ b/arch/mips/ralink/rt288x.c
|
||||
@@ -136,4 +136,8 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
|
||||
(id & CHIP_ID_REV_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT2880_SDRAM_BASE;
|
||||
+ soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
|
||||
}
|
|
@ -1,24 +0,0 @@
|
|||
From 8818e2d260e7f98fd5388f9ba56f54b788e175f0 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 27 Mar 2013 20:42:18 +0100
|
||||
Subject: [PATCH 2/5] MIPS: ralink: add pci group to struct ralink_pinmux
|
||||
|
||||
This will be used for RT3662/RT3883.
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/common.h | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -24,6 +24,9 @@ struct ralink_pinmux {
|
||||
int uart_shift;
|
||||
u32 uart_mask;
|
||||
void (*wdt_reset)(void);
|
||||
+ struct ralink_pinmux_grp *pci;
|
||||
+ int pci_shift;
|
||||
+ u32 pci_mask;
|
||||
};
|
||||
extern struct ralink_pinmux rt_pinmux;
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
From de85c6c3e2d5ed9c721a282d91af504a845e1fad Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 20:23:19 +0200
|
||||
Subject: [PATCH 125/137] MIPS: ralink: add memory definition for RT3883
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5182/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/rt3883.h | 4 ++++
|
||||
arch/mips/ralink/rt3883.c | 4 ++++
|
||||
2 files changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
|
||||
@@ -244,4 +244,8 @@
|
||||
#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
|
||||
#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
|
||||
|
||||
+#define RT3883_SDRAM_BASE 0x00000000
|
||||
+#define RT3883_MEM_SIZE_MIN 2
|
||||
+#define RT3883_MEM_SIZE_MAX 256
|
||||
+
|
||||
#endif /* _RT3883_REGS_H_ */
|
||||
--- a/arch/mips/ralink/rt3883.c
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -239,4 +239,8 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
name,
|
||||
(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
|
||||
(id & RT3883_REVID_ECO_ID_MASK));
|
||||
+
|
||||
+ soc_info->mem_base = RT3883_SDRAM_BASE;
|
||||
+ soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
|
||||
}
|
|
@ -1,42 +0,0 @@
|
|||
From fe26f3e7d1329fc2a5ac14808dbecb7d324d0a41 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 27 Mar 2013 20:56:22 +0100
|
||||
Subject: [PATCH 3/5] MIPS: ralink: process PCI pinmux group
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/pinmux.c | 14 +++++++++++++-
|
||||
1 file changed, 13 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/ralink/pinmux.c
|
||||
+++ b/arch/mips/ralink/pinmux.c
|
||||
@@ -29,7 +29,7 @@ void ralink_pinmux(void)
|
||||
const __be32 *wdt;
|
||||
struct device_node *np;
|
||||
struct property *prop;
|
||||
- const char *uart, *pin;
|
||||
+ const char *uart, *pci, *pin;
|
||||
u32 mode = 0;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
|
||||
@@ -76,5 +76,20 @@ void ralink_pinmux(void)
|
||||
if (wdt && *wdt && rt_pinmux.wdt_reset)
|
||||
rt_pinmux.wdt_reset();
|
||||
|
||||
+ pci = NULL;
|
||||
+ if (rt_pinmux.pci)
|
||||
+ of_property_read_string(np, "ralink,pcimux", &pci);
|
||||
+
|
||||
+ if (pci) {
|
||||
+ int m = ralink_mux_mask(pci, rt_pinmux.pci);
|
||||
+ mode &= ~(rt_pinmux.pci_mask << rt_pinmux.pci_shift);
|
||||
+ if (m) {
|
||||
+ mode |= (m << rt_pinmux.pci_shift);
|
||||
+ pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
|
||||
+ } else {
|
||||
+ pr_debug("pinmux: registered pcimux \"gpio\"\n");
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
|
||||
}
|
|
@ -1,58 +0,0 @@
|
|||
From 2c868d77c161ce7dea8facf203c155924d776c33 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 27 Mar 2013 20:50:40 +0100
|
||||
Subject: [PATCH 4/5] MIPS: ralink: add PCI pinmux group for RT3883
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/rt3883.c | 32 ++++++++++++++++++++++++++++++++
|
||||
1 file changed, 32 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/rt3883.c
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -113,6 +113,35 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
}, {0}
|
||||
};
|
||||
|
||||
+struct ralink_pinmux_grp pci_mux[] = {
|
||||
+ {
|
||||
+ .name = "pci-dev",
|
||||
+ .mask = 0,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host2",
|
||||
+ .mask = 1,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-host1",
|
||||
+ .mask = 2,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-fnc",
|
||||
+ .mask = 3,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {
|
||||
+ .name = "pci-gpio",
|
||||
+ .mask = 7,
|
||||
+ .gpio_first = RT3883_GPIO_PCI_AD0,
|
||||
+ .gpio_last = RT3883_GPIO_PCI_AD31,
|
||||
+ }, {0}
|
||||
+};
|
||||
+
|
||||
static void rt3883_wdt_reset(void)
|
||||
{
|
||||
u32 t;
|
||||
@@ -129,6 +158,9 @@ struct ralink_pinmux rt_pinmux = {
|
||||
.uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
|
||||
.uart_mask = RT3883_GPIO_MODE_GPIO,
|
||||
.wdt_reset = rt3883_wdt_reset,
|
||||
+ .pci = pci_mux,
|
||||
+ .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
|
||||
+ .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
|
||||
};
|
||||
|
||||
void __init ralink_clk_init(void)
|
|
@ -0,0 +1,58 @@
|
|||
From c1d35c42d697e9c28c817921a79c5f814529a4c6 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 14 Apr 2013 09:55:29 +0200
|
||||
Subject: [PATCH 126/137] MIPS: ralink: add memory definition for MT7620
|
||||
|
||||
Populate struct soc_info with the data that describes our RAM window.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5183/
|
||||
---
|
||||
arch/mips/include/asm/mach-ralink/mt7620.h | 8 ++++++++
|
||||
arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++
|
||||
2 files changed, 28 insertions(+)
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||||
@@ -50,6 +50,14 @@
|
||||
#define SYSCFG0_DRAM_TYPE_DDR1 1
|
||||
#define SYSCFG0_DRAM_TYPE_DDR2 2
|
||||
|
||||
+#define MT7620_DRAM_BASE 0x0
|
||||
+#define MT7620_SDRAM_SIZE_MIN 2
|
||||
+#define MT7620_SDRAM_SIZE_MAX 64
|
||||
+#define MT7620_DDR1_SIZE_MIN 32
|
||||
+#define MT7620_DDR1_SIZE_MAX 128
|
||||
+#define MT7620_DDR2_SIZE_MIN 32
|
||||
+#define MT7620_DDR2_SIZE_MAX 256
|
||||
+
|
||||
#define MT7620_GPIO_MODE_I2C BIT(0)
|
||||
#define MT7620_GPIO_MODE_UART0_SHIFT 2
|
||||
#define MT7620_GPIO_MODE_UART0_MASK 0x7
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_inf
|
||||
|
||||
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
|
||||
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
|
||||
+
|
||||
+ switch (dram_type) {
|
||||
+ case SYSCFG0_DRAM_TYPE_SDRAM:
|
||||
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
||||
+ break;
|
||||
+
|
||||
+ case SYSCFG0_DRAM_TYPE_DDR1:
|
||||
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
||||
+ break;
|
||||
+
|
||||
+ case SYSCFG0_DRAM_TYPE_DDR2:
|
||||
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
||||
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
||||
+ break;
|
||||
+ default:
|
||||
+ BUG();
|
||||
+ }
|
||||
+ soc_info->mem_base = MT7620_DRAM_BASE;
|
||||
}
|
|
@ -1,24 +0,0 @@
|
|||
From 79a01992e15216544dcfdc0be9f2f7695952d047 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Wed, 27 Mar 2013 20:59:26 +0100
|
||||
Subject: [PATCH 5/5] MIPS: ralink: add GPIO mode to RT3883 UART pinmux group
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/rt3883.c | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/rt3883.c
|
||||
+++ b/arch/mips/ralink/rt3883.c
|
||||
@@ -110,6 +110,11 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
.mask = RT3883_GPIO_MODE_GPIO_I2S,
|
||||
.gpio_first = RT3883_GPIO_7,
|
||||
.gpio_last = RT3883_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "gpio",
|
||||
+ .mask = RT3883_GPIO_MODE_GPIO,
|
||||
+ .gpio_first = RT3883_GPIO_7,
|
||||
+ .gpio_last = RT3883_GPIO_14,
|
||||
}, {0}
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
From 1618a00f709817cbcdebf038d0b5e251c8d67237 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 13 Apr 2013 15:15:51 +0200
|
||||
Subject: [PATCH 127/137] MIPS: ralink: make use of the new memory detection
|
||||
code
|
||||
|
||||
Call detect_memory_region() from plat_mem_setup() unless the size was already
|
||||
read from the system controller.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
Patchwork: http://patchwork.linux-mips.org/patch/5184/
|
||||
---
|
||||
arch/mips/ralink/of.c | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/init.h>
|
||||
+#include <linux/sizes.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bootmem.h>
|
||||
@@ -85,6 +86,14 @@ void __init plat_mem_setup(void)
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
__dt_setup_arch(&__dtb_start);
|
||||
+
|
||||
+ if (soc_info.mem_size)
|
||||
+ add_memory_region(soc_info.mem_base, soc_info.mem_size,
|
||||
+ BOOT_MEM_RAM);
|
||||
+ else
|
||||
+ detect_memory_region(soc_info.mem_base,
|
||||
+ soc_info.mem_size_min * SZ_1M,
|
||||
+ soc_info.mem_size_max * SZ_1M);
|
||||
}
|
||||
|
||||
static int __init plat_of_setup(void)
|
|
@ -1,82 +0,0 @@
|
|||
From 9830273b0c7f2e58a9226cc38bb0c4363e1fd8a2 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Sun, 7 Apr 2013 17:00:40 +0200
|
||||
Subject: [PATCH 1/3] MIPS: ralink: add cpu-feature-overrides.h for RT288x
|
||||
SoCs
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
.../asm/mach-ralink/rt288x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
arch/mips/ralink/Platform | 1 +
|
||||
2 files changed, 57 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT288x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT288X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 0
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 16
|
||||
+#define cpu_icache_line_size() 16
|
||||
+
|
||||
+#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -8,6 +8,7 @@ cflags-$(CONFIG_RALINK) += -I$(srctree)
|
||||
# Ralink RT288x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
|
||||
+cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
|
||||
|
||||
#
|
||||
# Ralink RT305x
|
|
@ -1,7 +1,7 @@
|
|||
From 806a489c720767f63bf5046c2ccd87ded9549c1c Mon Sep 17 00:00:00 2001
|
||||
From 5a2079532dfaf5762f658370ee7a0afb686f066e Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 16 Mar 2013 00:50:57 +0100
|
||||
Subject: [PATCH 104/121] MIPS: ralink: add pinmux driver
|
||||
Date: Mon, 22 Apr 2013 23:11:42 +0200
|
||||
Subject: [PATCH 128/137] MIPS: ralink: add pinmux driver
|
||||
|
||||
Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
|
||||
for this functionality with simple on/off bits. Building a full featured pinctrl
|
||||
|
@ -10,11 +10,10 @@ driver would be overkill.
|
|||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/common.h | 5 ++-
|
||||
arch/mips/ralink/common.h | 2 ++
|
||||
arch/mips/ralink/of.c | 2 ++
|
||||
arch/mips/ralink/pinmux.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/rt305x.c | 6 ++--
|
||||
5 files changed, 85 insertions(+), 6 deletions(-)
|
||||
4 files changed, 81 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/ralink/pinmux.c
|
||||
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
|
@ -26,23 +25,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
-obj-y := prom.o of.o reset.o clk.o irq.o
|
||||
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o
|
||||
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -22,9 +22,10 @@ struct ralink_pinmux {
|
||||
struct ralink_pinmux_grp *mode;
|
||||
struct ralink_pinmux_grp *uart;
|
||||
int uart_shift;
|
||||
+ u32 uart_mask;
|
||||
void (*wdt_reset)(void);
|
||||
};
|
||||
-extern struct ralink_pinmux gpio_pinmux;
|
||||
+extern struct ralink_pinmux rt_pinmux;
|
||||
|
||||
struct ralink_soc_info {
|
||||
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
|
||||
@@ -41,4 +42,6 @@ extern void prom_soc_init(struct ralink_
|
||||
@@ -50,4 +50,6 @@ extern void prom_soc_init(struct ralink_
|
||||
|
||||
__iomem void *plat_of_remap_node(const char *node);
|
||||
|
||||
|
@ -51,7 +38,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
#endif /* _RALINK_COMMON_H__ */
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -101,6 +101,8 @@ static int __init plat_of_setup(void)
|
||||
@@ -110,6 +110,8 @@ static int __init plat_of_setup(void)
|
||||
if (of_platform_populate(NULL, of_ids, NULL, NULL))
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
|
@ -102,7 +89,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ return;
|
||||
+
|
||||
+ of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
|
||||
+ int m = ralink_mux_mask(pin, rt_pinmux.mode);
|
||||
+ int m = ralink_mux_mask(pin, rt_gpio_pinmux.mode);
|
||||
+ if (m) {
|
||||
+ mode |= m;
|
||||
+ pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
|
||||
|
@ -112,7 +99,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }
|
||||
+
|
||||
+ of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
|
||||
+ int m = ralink_mux_mask(pin, rt_pinmux.mode);
|
||||
+ int m = ralink_mux_mask(pin, rt_gpio_pinmux.mode);
|
||||
+ if (m) {
|
||||
+ mode &= ~m;
|
||||
+ pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
|
||||
|
@ -123,10 +110,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+ of_property_read_string(np, "ralink,uartmux", &uart);
|
||||
+ if (uart) {
|
||||
+ int m = ralink_mux_mask(uart, rt_pinmux.uart);
|
||||
+ mode |= rt_pinmux.uart_mask << rt_pinmux.uart_shift;
|
||||
+ int m = ralink_mux_mask(uart, rt_gpio_pinmux.uart);
|
||||
+ mode |= rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift;
|
||||
+ if (m) {
|
||||
+ mode &= ~(m << rt_pinmux.uart_shift);
|
||||
+ mode &= ~(m << rt_gpio_pinmux.uart_shift);
|
||||
+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
|
||||
+ } else {
|
||||
+ pr_debug("pinmux: registered uartmux \"gpio\"\n");
|
||||
|
@ -134,33 +121,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ }
|
||||
+
|
||||
+ wdt = of_get_property(np, "ralink,wdtmux", NULL);
|
||||
+ if (wdt && *wdt && rt_pinmux.wdt_reset)
|
||||
+ rt_pinmux.wdt_reset();
|
||||
+ if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
|
||||
+ rt_gpio_pinmux.wdt_reset();
|
||||
+
|
||||
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
|
||||
+}
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -97,9 +97,6 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
.mask = RT305X_GPIO_MODE_GPIO_I2S,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
.gpio_last = RT305X_GPIO_14,
|
||||
- }, {
|
||||
- .name = "gpio",
|
||||
- .mask = RT305X_GPIO_MODE_GPIO,
|
||||
}, {0}
|
||||
};
|
||||
|
||||
@@ -114,10 +111,11 @@ void rt305x_wdt_reset(void)
|
||||
rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
|
||||
}
|
||||
|
||||
-struct ralink_pinmux gpio_pinmux = {
|
||||
+struct ralink_pinmux rt_pinmux = {
|
||||
.mode = mode_mux,
|
||||
.uart = uart_mux,
|
||||
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
|
||||
+ .uart_mask = RT305X_GPIO_MODE_GPIO,
|
||||
.wdt_reset = rt305x_wdt_reset,
|
||||
};
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
From 0eccf6e501337213d1de75dcf8f158d194ae0f77 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Sun, 7 Apr 2013 17:02:27 +0200
|
||||
Subject: [PATCH 2/3] MIPS: ralink: add cpu-feature-overrides.h for
|
||||
RT3x5x/RT5350 SoCs
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
.../asm/mach-ralink/rt305x/cpu-feature-overrides.h | 56 ++++++++++++++++++++
|
||||
arch/mips/ralink/Platform | 1 +
|
||||
2 files changed, 57 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,56 @@
|
||||
+/*
|
||||
+ * Ralink RT305x specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT305X_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -14,6 +14,7 @@ cflags-$(CONFIG_SOC_RT288X) += -I$(srctr
|
||||
# Ralink RT305x
|
||||
#
|
||||
load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
|
||||
|
||||
#
|
||||
# Ralink RT3883
|
|
@ -1,7 +1,7 @@
|
|||
From cdbc5a9dbd78a771edb6c211edbc677596cbd17f Mon Sep 17 00:00:00 2001
|
||||
From 1f307fd0fdca585d5c7c32963e8a8a6f38d8a78c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sat, 23 Mar 2013 19:44:41 +0100
|
||||
Subject: [PATCH 113/121] MIPS: ralink: add support for periodic timer irq
|
||||
Subject: [PATCH 129/137] MIPS: ralink: add support for periodic timer irq
|
||||
|
||||
Adds a driver for the periodic timer found on Ralink SoC.
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
From f22c157f44c93d61058d2e2aa5626ee2899fde5a Mon Sep 17 00:00:00 2001
|
||||
From 007ab7fe49bfcaa220372260eedeb4eed51f1631 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Jan 2013 18:24:34 +0100
|
||||
Subject: [PATCH 114/121] GPIO: MIPS: ralink: adds ralink gpio support
|
||||
Subject: [PATCH 130/137] GPIO: MIPS: ralink: adds ralink gpio support
|
||||
|
||||
Add gpio driver for Ralink SoC. This driver makes the gpio core on
|
||||
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
|
|
@ -1,81 +0,0 @@
|
|||
From 4cca623b74420aacf656b968fde29aace96ae3db Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <juhosg@openwrt.org>
|
||||
Date: Sun, 7 Apr 2013 16:57:30 +0200
|
||||
Subject: [PATCH 3/3] MIPS: ralink: add cpu-feature-overrides.h for
|
||||
RT3662/3883 SoCs
|
||||
|
||||
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
.../asm/mach-ralink/rt3883/cpu-feature-overrides.h | 55 ++++++++++++++++++++
|
||||
arch/mips/ralink/Platform | 1 +
|
||||
2 files changed, 56 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 specific CPU feature overrides
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * This file was derived from: include/asm-mips/cpu-features.h
|
||||
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
||||
+ * Copyright (C) 2004 Maciej W. Rozycki
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+#define _RT3883_CPU_FEATURE_OVERRIDES_H
|
||||
+
|
||||
+#define cpu_has_tlb 1
|
||||
+#define cpu_has_4kex 1
|
||||
+#define cpu_has_3k_cache 0
|
||||
+#define cpu_has_4k_cache 1
|
||||
+#define cpu_has_tx39_cache 0
|
||||
+#define cpu_has_sb1_cache 0
|
||||
+#define cpu_has_fpu 0
|
||||
+#define cpu_has_32fpr 0
|
||||
+#define cpu_has_counter 1
|
||||
+#define cpu_has_watch 1
|
||||
+#define cpu_has_divec 1
|
||||
+
|
||||
+#define cpu_has_prefetch 1
|
||||
+#define cpu_has_ejtag 1
|
||||
+#define cpu_has_llsc 1
|
||||
+
|
||||
+#define cpu_has_mips16 1
|
||||
+#define cpu_has_mdmx 0
|
||||
+#define cpu_has_mips3d 0
|
||||
+#define cpu_has_smartmips 0
|
||||
+
|
||||
+#define cpu_has_mips32r1 1
|
||||
+#define cpu_has_mips32r2 1
|
||||
+#define cpu_has_mips64r1 0
|
||||
+#define cpu_has_mips64r2 0
|
||||
+
|
||||
+#define cpu_has_dsp 1
|
||||
+#define cpu_has_mipsmt 0
|
||||
+
|
||||
+#define cpu_has_64bits 0
|
||||
+#define cpu_has_64bit_zero_reg 0
|
||||
+#define cpu_has_64bit_gp_regs 0
|
||||
+#define cpu_has_64bit_addresses 0
|
||||
+
|
||||
+#define cpu_dcache_line_size() 32
|
||||
+#define cpu_icache_line_size() 32
|
||||
+
|
||||
+#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
|
||||
--- a/arch/mips/ralink/Platform
|
||||
+++ b/arch/mips/ralink/Platform
|
||||
@@ -20,6 +20,7 @@ cflags-$(CONFIG_SOC_RT305X) += -I$(srctr
|
||||
# Ralink RT3883
|
||||
#
|
||||
load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
|
||||
+cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
|
||||
|
||||
#
|
||||
# Ralink MT7620
|
|
@ -1,7 +1,7 @@
|
|||
e8c5ebbd743dac63178807c0f68fe1b75680474a3 Mon Sep 17 00:00:00 2001
|
||||
From 32c1cff4c75925a0bbd305e85ed4adb30140cd42 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Wed, 30 Jan 2013 17:58:15 +0100
|
||||
Subject: [PATCH 115/121] SPI: ralink: add Ralink SoC spi driver
|
||||
Date: Mon, 22 Apr 2013 23:16:18 +0200
|
||||
Subject: [PATCH 131/137] SPI: ralink: add Ralink SoC spi driver
|
||||
|
||||
Add the driver needed to make SPI work on Ralink SoC.
|
||||
|
|
@ -1,222 +0,0 @@
|
|||
--- a/drivers/net/ethernet/ramips/ramips_main.c
|
||||
+++ b/drivers/net/ethernet/ramips/ramips_main.c
|
||||
@@ -28,6 +28,7 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_net.h>
|
||||
+#include <linux/of_mdio.h>
|
||||
|
||||
#include "ramips_eth.h"
|
||||
|
||||
@@ -406,12 +407,25 @@ ramips_mdio_reset(struct mii_bus *bus)
|
||||
static int
|
||||
ramips_mdio_init(struct raeth_priv *re)
|
||||
{
|
||||
+ struct device_node *mii_np;
|
||||
int err;
|
||||
- int i;
|
||||
+
|
||||
+ mii_np = of_get_child_by_name(re->of_node, "mdio-bus");
|
||||
+ if (!mii_np) {
|
||||
+ dev_err(re->parent, "no %s child node found", "mdio-bus");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ if (!of_device_is_available(mii_np)) {
|
||||
+ err = 0;
|
||||
+ goto err_put_node;
|
||||
+ }
|
||||
|
||||
re->mii_bus = mdiobus_alloc();
|
||||
- if (re->mii_bus == NULL)
|
||||
- return -ENOMEM;
|
||||
+ if (re->mii_bus == NULL) {
|
||||
+ err = -ENOMEM;
|
||||
+ goto err_put_node;
|
||||
+ }
|
||||
|
||||
re->mii_bus->name = "ramips_mdio";
|
||||
re->mii_bus->read = ramips_mdio_read;
|
||||
@@ -422,12 +436,7 @@ ramips_mdio_init(struct raeth_priv *re)
|
||||
re->mii_bus->parent = re->parent;
|
||||
|
||||
snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
|
||||
- re->mii_bus->phy_mask = 0;
|
||||
-
|
||||
- for (i = 0; i < PHY_MAX_ADDR; i++)
|
||||
- re->mii_irq[i] = PHY_POLL;
|
||||
-
|
||||
- err = mdiobus_register(re->mii_bus);
|
||||
+ err = of_mdiobus_register(re->mii_bus, mii_np);
|
||||
if (err)
|
||||
goto err_free_bus;
|
||||
|
||||
@@ -435,13 +444,20 @@ ramips_mdio_init(struct raeth_priv *re)
|
||||
|
||||
err_free_bus:
|
||||
kfree(re->mii_bus);
|
||||
+err_put_node:
|
||||
+ of_node_put(mii_np);
|
||||
+ re->mii_bus = NULL;
|
||||
return err;
|
||||
}
|
||||
|
||||
static void
|
||||
ramips_mdio_cleanup(struct raeth_priv *re)
|
||||
{
|
||||
+ if (!re->mii_bus)
|
||||
+ return;
|
||||
+
|
||||
mdiobus_unregister(re->mii_bus);
|
||||
+ of_node_put(re->mii_bus->dev.of_node);
|
||||
kfree(re->mii_bus);
|
||||
}
|
||||
|
||||
@@ -474,106 +490,86 @@ ramips_phy_link_adjust(struct net_device
|
||||
}
|
||||
|
||||
static int
|
||||
-ramips_phy_connect_multi(struct raeth_priv *re)
|
||||
+ramips_phy_connect_by_node(struct raeth_priv *re, struct device_node *phy_node)
|
||||
{
|
||||
- struct net_device *netdev = re->netdev;
|
||||
- struct phy_device *phydev = NULL;
|
||||
- int phy_addr;
|
||||
- int ret = 0;
|
||||
-
|
||||
- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
|
||||
- if (!(re->phy_mask & (1 << phy_addr)))
|
||||
- continue;
|
||||
-
|
||||
- if (re->mii_bus->phy_map[phy_addr] == NULL)
|
||||
- continue;
|
||||
+ struct phy_device *phydev;
|
||||
+ int phy_mode;
|
||||
|
||||
- RADEBUG("%s: PHY found at %s, uid=%08x\n",
|
||||
- netdev->name,
|
||||
- dev_name(&re->mii_bus->phy_map[phy_addr]->dev),
|
||||
- re->mii_bus->phy_map[phy_addr]->phy_id);
|
||||
-
|
||||
- if (phydev == NULL)
|
||||
- phydev = re->mii_bus->phy_map[phy_addr];
|
||||
- }
|
||||
-
|
||||
- if (!phydev) {
|
||||
- netdev_err(netdev, "no PHY found with phy_mask=%08x\n",
|
||||
- re->phy_mask);
|
||||
- return -ENODEV;
|
||||
+ phy_mode = of_get_phy_mode(re->of_node);
|
||||
+ if (phy_mode < 0) {
|
||||
+ dev_err(re->parent, "incorrect phy-mode\n");
|
||||
+ return -EINVAL;
|
||||
}
|
||||
|
||||
- re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev),
|
||||
- ramips_phy_link_adjust, 0, re->phy_if_mode);
|
||||
-
|
||||
- if (IS_ERR(re->phy_dev)) {
|
||||
- netdev_err(netdev, "could not connect to PHY at %s\n",
|
||||
- dev_name(&phydev->dev));
|
||||
+ phydev = of_phy_connect(re->netdev, phy_node, ramips_phy_link_adjust,
|
||||
+ 0, phy_mode);
|
||||
+ if (IS_ERR(phydev)) {
|
||||
+ dev_err(re->parent, "could not connect to PHY\n");
|
||||
return PTR_ERR(re->phy_dev);
|
||||
}
|
||||
|
||||
phydev->supported &= PHY_GBIT_FEATURES;
|
||||
phydev->advertising = phydev->supported;
|
||||
|
||||
- RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n",
|
||||
- netdev->name, dev_name(&phydev->dev),
|
||||
- phydev->phy_id, phydev->drv->name);
|
||||
+ dev_info(re->parent,
|
||||
+ "connected to PHY at %s [uid=%08x, driver=%s]\n",
|
||||
+ dev_name(&phydev->dev), phydev->phy_id,
|
||||
+ phydev->drv->name);
|
||||
|
||||
+ re->phy_dev = phydev;
|
||||
re->link = 0;
|
||||
re->speed = 0;
|
||||
re->duplex = -1;
|
||||
re->rx_fc = 0;
|
||||
re->tx_fc = 0;
|
||||
|
||||
- return ret;
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
-ramips_phy_connect_fixed(struct raeth_priv *re)
|
||||
+ramips_phy_connect_fixed(struct raeth_priv *re, const __be32 *link, int size)
|
||||
{
|
||||
- if (!re->speed) {
|
||||
- const __be32 *link;
|
||||
- int size;
|
||||
-
|
||||
- link = of_get_property(re->of_node,
|
||||
- "ralink,fixed-link", &size);
|
||||
- if (!link || size != (4 * sizeof(*link)))
|
||||
- return -ENOENT;
|
||||
-
|
||||
- re->speed = be32_to_cpup(link++);
|
||||
- re->duplex = be32_to_cpup(link++);
|
||||
- re->tx_fc = be32_to_cpup(link++);
|
||||
- re->rx_fc = be32_to_cpup(link++);
|
||||
+ if (size != (4 * sizeof(*link))) {
|
||||
+ dev_err(re->parent, "invalid fixed-link property\n");
|
||||
+ return -EINVAL;
|
||||
}
|
||||
|
||||
+ re->speed = be32_to_cpup(link++);
|
||||
+ re->duplex = be32_to_cpup(link++);
|
||||
+ re->tx_fc = be32_to_cpup(link++);
|
||||
+ re->rx_fc = be32_to_cpup(link++);
|
||||
+
|
||||
switch (re->speed) {
|
||||
case SPEED_10:
|
||||
case SPEED_100:
|
||||
case SPEED_1000:
|
||||
break;
|
||||
default:
|
||||
- netdev_err(re->netdev, "invalid speed specified\n");
|
||||
+ dev_err(re->parent, "invalid link speed: %d\n", re->speed);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- pr_info("%s: using fixed link parameters\n", re->netdev->name);
|
||||
+ dev_info(re->parent, "using fixed link parameters\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
ramips_phy_connect(struct raeth_priv *re)
|
||||
{
|
||||
- const __be32 *mask;
|
||||
-
|
||||
- mask = of_get_property(re->of_node, "ralink,phy-mask", NULL);
|
||||
- re->phy_if_mode = of_get_phy_mode(re->of_node);
|
||||
-
|
||||
- if (!re->phy_if_mode || !mask)
|
||||
- return ramips_phy_connect_fixed(re);
|
||||
-
|
||||
- re->phy_mask = be32_to_cpup(mask);
|
||||
- return ramips_phy_connect_multi(re);
|
||||
+ struct device_node *phy_node;
|
||||
+ const __be32 *p32;
|
||||
+ int size;
|
||||
+
|
||||
+ phy_node = of_parse_phandle(re->of_node, "phy-handle", 0);
|
||||
+ if (phy_node)
|
||||
+ return ramips_phy_connect_by_node(re, phy_node);
|
||||
+
|
||||
+ p32 = of_get_property(re->of_node, "ralink,fixed-link", &size);
|
||||
+ if (p32)
|
||||
+ return ramips_phy_connect_fixed(re, p32, size);
|
||||
|
||||
+ dev_err(re->parent, "unable to get connection type\n");
|
||||
+ return -EINVAL;
|
||||
}
|
||||
|
||||
static void
|
|
@ -1,7 +1,7 @@
|
|||
From 6ffb42870411ca082e8e46d96d72bc5d8881ce8d Mon Sep 17 00:00:00 2001
|
||||
From 15bcdbd78abacbe0986a1904d2e2b5dcfe780b5b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Jan 2013 16:01:07 +0100
|
||||
Subject: [PATCH 116/121] serial: of: allow au1x00 and rt288x to load from OF
|
||||
Subject: [PATCH 132/137] serial: of: allow au1x00 and rt288x to load from OF
|
||||
|
||||
In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
|
||||
to default the iotype to UPIO_AU.
|
|
@ -1,7 +1,7 @@
|
|||
From c1e24bf32404bec0032221b9ea37d6fd8c45dbdd Mon Sep 17 00:00:00 2001
|
||||
From 6471ee7bbf3f8b70267ba1dc93f067e18803c246 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 15 Mar 2013 18:16:01 +0100
|
||||
Subject: [PATCH 117/121] serial: ralink: adds mt7620 serial
|
||||
Subject: [PATCH 133/137] serial: ralink: adds mt7620 serial
|
||||
|
||||
Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
From 028f340b63bf722e8807b31ef955484acf2cce47 Mon Sep 17 00:00:00 2001
|
||||
From 55e9ae6a23cb799b7c1d402e1cfda11a6bd1e86e Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 18:27:29 +0100
|
||||
Subject: [PATCH 118/121] PCI: MIPS: adds rt2880 pci support
|
||||
Subject: [PATCH 134/137] PCI: MIPS: adds rt2880 pci support
|
||||
|
||||
Add support for the pci found on the rt2880 SoC.
|
||||
|
|
@ -1,44 +1,61 @@
|
|||
--- a/arch/mips/pci/pci-rt3883.c
|
||||
From 2a5dccdb00d85a6ad6111d7a2b13f9f4fae35838 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Thu, 21 Mar 2013 17:34:08 +0100
|
||||
Subject: [PATCH 135/137] PCI: MIPS: adds rt3883 pci support
|
||||
|
||||
Add support for the pcie found on the rt3883 SoC.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/pci/Makefile | 1 +
|
||||
arch/mips/pci/pci-rt3883.c | 640 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
arch/mips/ralink/Kconfig | 1 +
|
||||
3 files changed, 642 insertions(+)
|
||||
create mode 100644 arch/mips/pci/pci-rt3883.c
|
||||
|
||||
--- a/arch/mips/pci/Makefile
|
||||
+++ b/arch/mips/pci/Makefile
|
||||
@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
|
||||
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
|
||||
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
|
||||
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
|
||||
+obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
|
||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/pci/pci-rt3883.c
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
- * Ralink RT3883 SoC PCI support
|
||||
@@ -0,0 +1,640 @@
|
||||
+/*
|
||||
+ * Ralink RT3662/RT3883 SoC PCI support
|
||||
*
|
||||
- * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ *
|
||||
+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
*
|
||||
@@ -16,52 +16,82 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
+ *
|
||||
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach-ralink/rt3883.h>
|
||||
-#include <asm/mach-ralink/rt3883_regs.h>
|
||||
+
|
||||
+#include <asm/mach-ralink/rt3883.h>
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#define RT3883_MEMORY_BASE 0x00000000
|
||||
#define RT3883_MEMORY_SIZE 0x02000000
|
||||
|
||||
-#define RT3883_PCI_MEM_BASE 0x20000000
|
||||
-#define RT3883_PCI_MEM_SIZE 0x10000000
|
||||
-#define RT3883_PCI_IO_BASE 0x10160000
|
||||
-#define RT3883_PCI_IO_SIZE 0x00010000
|
||||
-
|
||||
-#define RT3883_PCI_REG_PCICFG_ADDR 0x00
|
||||
-#define RT3883_PCI_REG_PCIRAW_ADDR 0x04
|
||||
-#define RT3883_PCI_REG_PCIINT_ADDR 0x08
|
||||
-#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
|
||||
-#define RT3833_PCI_PCIINT_PCIE BIT(20)
|
||||
-#define RT3833_PCI_PCIINT_PCI1 BIT(19)
|
||||
-#define RT3833_PCI_PCIINT_PCI0 BIT(18)
|
||||
+
|
||||
+#define RT3883_MEMORY_BASE 0x00000000
|
||||
+#define RT3883_MEMORY_SIZE 0x02000000
|
||||
+
|
||||
+#define RT3883_PCI_REG_PCICFG 0x00
|
||||
+#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
|
||||
+#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
|
||||
|
@ -46,34 +63,26 @@
|
|||
+#define RT3883_PCI_REG_PCIRAW 0x04
|
||||
+#define RT3883_PCI_REG_PCIINT 0x08
|
||||
+#define RT3883_PCI_REG_PCIENA 0x0c
|
||||
|
||||
-#define RT3883_PCI_REG_CONFIG_ADDR 0x20
|
||||
-#define RT3883_PCI_REG_CONFIG_DATA 0x24
|
||||
+
|
||||
+#define RT3883_PCI_REG_CFGADDR 0x20
|
||||
+#define RT3883_PCI_REG_CFGDATA 0x24
|
||||
#define RT3883_PCI_REG_MEMBASE 0x28
|
||||
#define RT3883_PCI_REG_IOBASE 0x2c
|
||||
#define RT3883_PCI_REG_ARBCTL 0x80
|
||||
|
||||
#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
|
||||
-#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
|
||||
-#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
|
||||
+#define RT3883_PCI_REG_MEMBASE 0x28
|
||||
+#define RT3883_PCI_REG_IOBASE 0x2c
|
||||
+#define RT3883_PCI_REG_ARBCTL 0x80
|
||||
+
|
||||
+#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
|
||||
+#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
|
||||
+#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
|
||||
#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
|
||||
#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
|
||||
#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
|
||||
#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
|
||||
|
||||
-static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
-static void __iomem *rt3883_pci_base;
|
||||
-static DEFINE_SPINLOCK(rt3883_pci_lock);
|
||||
+#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
|
||||
+#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
|
||||
+#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
|
||||
+#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
|
||||
+
|
||||
+#define RT3883_PCI_MODE_NONE 0
|
||||
+#define RT3883_PCI_MODE_PCI BIT(0)
|
||||
+#define RT3883_PCI_MODE_PCIE BIT(1)
|
||||
+#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
|
||||
|
||||
-static inline u32 rt3883_pci_rr(unsigned reg)
|
||||
+
|
||||
+#define RT3883_PCI_IRQ_COUNT 32
|
||||
+
|
||||
+#define RT3883_P2P_BR_DEVNUM 1
|
||||
|
@ -94,8 +103,7 @@
|
|||
+
|
||||
+static inline struct rt3883_pci_controller *
|
||||
+pci_bus_to_rt3883_controller(struct pci_bus *bus)
|
||||
{
|
||||
- return readl(rt3883_pci_base + reg);
|
||||
+{
|
||||
+ struct pci_controller *hose;
|
||||
+
|
||||
+ hose = (struct pci_controller *) bus->sysdata;
|
||||
|
@ -106,168 +114,115 @@
|
|||
+ unsigned reg)
|
||||
+{
|
||||
+ return ioread32(rpc->base + reg);
|
||||
}
|
||||
|
||||
-static inline void rt3883_pci_wr(u32 val, unsigned reg)
|
||||
+}
|
||||
+
|
||||
+static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
|
||||
+ u32 val, unsigned reg)
|
||||
{
|
||||
- writel(val, rt3883_pci_base + reg);
|
||||
+{
|
||||
+ iowrite32(val, rpc->base + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
@@ -71,7 +101,8 @@ static inline u32 rt3883_pci_get_cfgaddr
|
||||
0x80000000);
|
||||
}
|
||||
|
||||
-static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
|
||||
+}
|
||||
+
|
||||
+static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
+ unsigned int func, unsigned int where)
|
||||
+{
|
||||
+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
|
||||
+ 0x80000000);
|
||||
+}
|
||||
+
|
||||
+static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
|
||||
+ unsigned bus, unsigned slot,
|
||||
unsigned func, unsigned reg)
|
||||
{
|
||||
unsigned long flags;
|
||||
@@ -80,15 +111,16 @@ static u32 rt3883_pci_read_u32(unsigned
|
||||
|
||||
address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
|
||||
- spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
- ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+ unsigned func, unsigned reg)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 ret;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
|
||||
+ unsigned bus, unsigned slot,
|
||||
unsigned func, unsigned reg, u32 val)
|
||||
{
|
||||
unsigned long flags;
|
||||
@@ -96,84 +128,61 @@ static void rt3883_pci_write_u32(unsigne
|
||||
|
||||
address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
|
||||
- spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
- rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
|
||||
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+ unsigned func, unsigned reg, u32 val)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+
|
||||
+ address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
}
|
||||
|
||||
static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
u32 pending;
|
||||
|
||||
- pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
|
||||
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ u32 pending;
|
||||
+
|
||||
+ rpc = irq_get_handler_data(irq);
|
||||
+
|
||||
+ pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
|
||||
if (!pending) {
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
- if (pending & RT3833_PCI_PCIINT_PCI0)
|
||||
- generic_handle_irq(RT3883_PCI_IRQ_PCI0);
|
||||
+
|
||||
+ if (!pending) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ while (pending) {
|
||||
+ unsigned bit = __ffs(pending);
|
||||
|
||||
- if (pending & RT3833_PCI_PCIINT_PCI1)
|
||||
- generic_handle_irq(RT3883_PCI_IRQ_PCI1);
|
||||
+
|
||||
+ irq = irq_find_mapping(rpc->irq_domain, bit);
|
||||
+ generic_handle_irq(irq);
|
||||
|
||||
- if (pending & RT3833_PCI_PCIINT_PCIE)
|
||||
- generic_handle_irq(RT3883_PCI_IRQ_PCIE);
|
||||
+
|
||||
+ pending &= ~BIT(bit);
|
||||
+ }
|
||||
}
|
||||
|
||||
static void rt3883_pci_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
- int irq = d->irq;
|
||||
- u32 mask;
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
u32 t;
|
||||
|
||||
- switch (irq) {
|
||||
- case RT3883_PCI_IRQ_PCI0:
|
||||
- mask = RT3833_PCI_PCIINT_PCI0;
|
||||
- break;
|
||||
- case RT3883_PCI_IRQ_PCI1:
|
||||
- mask = RT3833_PCI_PCIINT_PCI1;
|
||||
- break;
|
||||
- case RT3883_PCI_IRQ_PCIE:
|
||||
- mask = RT3833_PCI_PCIINT_PCIE;
|
||||
- break;
|
||||
- default:
|
||||
- BUG();
|
||||
- }
|
||||
+ u32 t;
|
||||
+
|
||||
+ rpc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
- t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
- rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+ rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
|
||||
/* flush write */
|
||||
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
}
|
||||
|
||||
static void rt3883_pci_irq_mask(struct irq_data *d)
|
||||
{
|
||||
- int irq = d->irq;
|
||||
- u32 mask;
|
||||
+}
|
||||
+
|
||||
+static void rt3883_pci_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
u32 t;
|
||||
|
||||
- switch (irq) {
|
||||
- case RT3883_PCI_IRQ_PCI0:
|
||||
- mask = RT3833_PCI_PCIINT_PCI0;
|
||||
- break;
|
||||
- case RT3883_PCI_IRQ_PCI1:
|
||||
- mask = RT3833_PCI_PCIINT_PCI1;
|
||||
- break;
|
||||
- case RT3883_PCI_IRQ_PCIE:
|
||||
- mask = RT3833_PCI_PCIINT_PCIE;
|
||||
- break;
|
||||
- default:
|
||||
- BUG();
|
||||
- }
|
||||
+ u32 t;
|
||||
+
|
||||
+ rpc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
- t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
- rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
+ rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
|
||||
/* flush write */
|
||||
- rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
|
||||
}
|
||||
|
||||
static struct irq_chip rt3883_pci_irq_chip = {
|
||||
@@ -183,36 +192,84 @@ static struct irq_chip rt3883_pci_irq_ch
|
||||
.irq_mask_ack = rt3883_pci_irq_mask,
|
||||
};
|
||||
|
||||
-static void __init rt3883_pci_irq_init(void)
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip rt3883_pci_irq_chip = {
|
||||
+ .name = "RT3883 PCI",
|
||||
+ .irq_mask = rt3883_pci_irq_mask,
|
||||
+ .irq_unmask = rt3883_pci_irq_unmask,
|
||||
+ .irq_mask_ack = rt3883_pci_irq_mask,
|
||||
+};
|
||||
+
|
||||
+static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
|
||||
+ irq_hw_number_t hw)
|
||||
{
|
||||
- int i;
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, d->host_data);
|
||||
+
|
||||
|
@ -299,15 +254,10 @@
|
|||
+ err = -EINVAL;
|
||||
+ goto err_put_intc;
|
||||
+ }
|
||||
|
||||
/* disable all interrupts */
|
||||
- rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
|
||||
+
|
||||
+ /* disable all interrupts */
|
||||
+ rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
|
||||
|
||||
- for (i = RT3883_PCI_IRQ_BASE;
|
||||
- i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
|
||||
- irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
|
||||
- handle_level_irq);
|
||||
+
|
||||
+ rpc->irq_domain =
|
||||
+ irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
|
||||
+ &rt3883_pci_irq_domain_ops,
|
||||
|
@ -316,9 +266,8 @@
|
|||
+ dev_err(dev, "unable to add IRQ domain\n");
|
||||
+ err = -ENODEV;
|
||||
+ goto err_put_intc;
|
||||
}
|
||||
|
||||
- irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
|
||||
+ }
|
||||
+
|
||||
+ irq_set_handler_data(irq, rpc);
|
||||
+ irq_set_chained_handler(irq, rt3883_pci_irq_handler);
|
||||
+
|
||||
|
@ -327,133 +276,104 @@
|
|||
+err_put_intc:
|
||||
+ of_node_put(intc_np);
|
||||
+ return err;
|
||||
}
|
||||
|
||||
static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 *val)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
unsigned long flags;
|
||||
u32 address;
|
||||
u32 data;
|
||||
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(bus);
|
||||
+
|
||||
+ if (!rpc->pcie_ready && bus->number == 1)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
PCI_FUNC(devfn), where);
|
||||
|
||||
- spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
- data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
@@ -232,16 +289,22 @@ static int rt3883_pci_config_read(struct
|
||||
static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *val = (data >> ((where & 3) << 3)) & 0xffff;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ *val = data;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where, int size, u32 val)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
unsigned long flags;
|
||||
u32 address;
|
||||
u32 data;
|
||||
|
||||
+ unsigned long flags;
|
||||
+ u32 address;
|
||||
+ u32 data;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(bus);
|
||||
+
|
||||
+ if (!rpc->pcie_ready && bus->number == 1)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
PCI_FUNC(devfn), where);
|
||||
|
||||
- spin_lock_irqsave(&rt3883_pci_lock, flags);
|
||||
- rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
|
||||
- data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
|
||||
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
|
||||
+ PCI_FUNC(devfn), where);
|
||||
+
|
||||
+ spin_lock_irqsave(&rpc->lock, flags);
|
||||
+ rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
|
||||
+ data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
@@ -257,8 +320,8 @@ static int rt3883_pci_config_write(struc
|
||||
break;
|
||||
}
|
||||
|
||||
- rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
|
||||
- spin_unlock_irqrestore(&rt3883_pci_lock, flags);
|
||||
+
|
||||
+ switch (size) {
|
||||
+ case 1:
|
||||
+ data = (data & ~(0xff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
|
||||
+ (val << ((where & 3) << 3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ data = val;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
|
||||
+ spin_unlock_irqrestore(&rpc->lock, flags);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
@@ -268,220 +331,310 @@ static struct pci_ops rt3883_pci_ops = {
|
||||
.write = rt3883_pci_config_write,
|
||||
};
|
||||
|
||||
-static struct resource rt3883_pci_mem_resource = {
|
||||
- .name = "PCI MEM space",
|
||||
- .start = RT3883_PCI_MEM_BASE,
|
||||
- .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
|
||||
- .flags = IORESOURCE_MEM,
|
||||
-};
|
||||
-
|
||||
-static struct resource rt3883_pci_io_resource = {
|
||||
- .name = "PCI IO space",
|
||||
- .start = RT3883_PCI_IO_BASE,
|
||||
- .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
|
||||
- .flags = IORESOURCE_IO,
|
||||
-};
|
||||
-
|
||||
-static struct pci_controller rt3883_pci_controller = {
|
||||
- .pci_ops = &rt3883_pci_ops,
|
||||
- .mem_resource = &rt3883_pci_mem_resource,
|
||||
- .io_resource = &rt3883_pci_io_resource,
|
||||
-};
|
||||
-
|
||||
-static void rt3883_pci_preinit(unsigned mode)
|
||||
+
|
||||
+ return PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops rt3883_pci_ops = {
|
||||
+ .read = rt3883_pci_config_read,
|
||||
+ .write = rt3883_pci_config_write,
|
||||
+};
|
||||
+
|
||||
+static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
|
||||
{
|
||||
u32 syscfg1;
|
||||
u32 rstctrl;
|
||||
u32 clkcfg1;
|
||||
+{
|
||||
+ u32 syscfg1;
|
||||
+ u32 rstctrl;
|
||||
+ u32 clkcfg1;
|
||||
+ u32 t;
|
||||
+
|
||||
+ rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
+ syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
|
||||
+ clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
- u32 val;
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ rstctrl |= RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
|
||||
- val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
|
||||
- val &= ~(0x30);
|
||||
- val |= (2 << 4);
|
||||
- rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
|
||||
-
|
||||
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
- val &= ~BIT(31);
|
||||
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
-
|
||||
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
- val &= 0x80ffffff;
|
||||
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
-
|
||||
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
- val |= 0xa << 24;
|
||||
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
|
||||
-
|
||||
- val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
- val |= BIT(31);
|
||||
- rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+
|
||||
+ /* setup PCI PAD drive mode */
|
||||
+ syscfg1 &= ~(0x30);
|
||||
+ syscfg1 |= (2 << 4);
|
||||
|
@ -474,67 +394,44 @@
|
|||
+ t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
+ t |= BIT(31);
|
||||
+ rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
|
||||
|
||||
msleep(50);
|
||||
+
|
||||
+ msleep(50);
|
||||
+
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
}
|
||||
|
||||
- syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
|
||||
- syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
|
||||
- RT3883_SYSCFG1_PCI_HOST_MODE);
|
||||
-
|
||||
- rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
|
||||
- rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
|
||||
-
|
||||
- clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
|
||||
- clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
|
||||
- RT3883_CLKCFG1_PCIE_CLK_EN);
|
||||
+ }
|
||||
+
|
||||
+ syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
|
||||
+
|
||||
+ clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
|
||||
|
||||
if (mode & RT3883_PCI_MODE_PCI) {
|
||||
- syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
|
||||
clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
|
||||
rstctrl &= ~RT3883_RSTCTRL_PCI;
|
||||
}
|
||||
+
|
||||
if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
- syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
|
||||
- RT3883_SYSCFG1_PCIE_RC_MODE;
|
||||
clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
}
|
||||
|
||||
- rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
- rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
- rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
|
||||
+ if (mode & RT3883_PCI_MODE_PCI) {
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCI;
|
||||
+ }
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
|
||||
+ rstctrl &= ~RT3883_RSTCTRL_PCIE;
|
||||
+ }
|
||||
+
|
||||
+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
|
||||
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
|
||||
+ rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
|
||||
|
||||
msleep(500);
|
||||
-}
|
||||
|
||||
-static int rt3883_pcie_ready(void)
|
||||
-{
|
||||
- u32 status;
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ /*
|
||||
+ * setup the device number of the P2P bridge
|
||||
+ * and de-assert the reset line
|
||||
+ */
|
||||
+ t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
|
||||
+ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
|
||||
|
||||
+
|
||||
+ /* flush write */
|
||||
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
|
||||
msleep(500);
|
||||
|
||||
- status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
|
||||
- if (status & BIT(0))
|
||||
- return 0;
|
||||
+ msleep(500);
|
||||
+
|
||||
+ if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
+ msleep(500);
|
||||
+
|
||||
|
@ -564,8 +461,7 @@
|
|||
+ /* enable PCI arbiter */
|
||||
+ rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
|
||||
+}
|
||||
|
||||
- /* TODO: reset PCIe and turn off PCIe clock */
|
||||
+
|
||||
+static inline void
|
||||
+rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
|
||||
+ int bus, int slot)
|
||||
|
@ -574,27 +470,24 @@
|
|||
+
|
||||
+ for (i = 0; i < 16; i++) {
|
||||
+ u32 val;
|
||||
|
||||
- return -ENODEV;
|
||||
+
|
||||
+ val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
|
||||
+ pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
|
||||
+ bus, slot, i << 2, val);
|
||||
+ }
|
||||
}
|
||||
|
||||
-void __init rt3883_pci_init(unsigned mode)
|
||||
+}
|
||||
+
|
||||
+static int rt3883_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res;
|
||||
+ struct device_node *child;
|
||||
u32 val;
|
||||
int err;
|
||||
+ u32 val;
|
||||
+ int err;
|
||||
+ int mode;
|
||||
|
||||
- rt3883_pci_preinit(mode);
|
||||
+
|
||||
+ rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
|
||||
+ if (!rpc)
|
||||
+ return -ENOMEM;
|
||||
|
@ -627,11 +520,7 @@
|
|||
+ of_node_full_name(child));
|
||||
+ continue;
|
||||
+ }
|
||||
|
||||
- rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
|
||||
- if (rt3883_pci_base == NULL) {
|
||||
- pr_err("failed to ioremap PCI registers\n");
|
||||
- return;
|
||||
+
|
||||
+ switch (slot) {
|
||||
+ case 1:
|
||||
+ mode |= RT3883_PCI_MODE_PCIE;
|
||||
|
@ -642,37 +531,24 @@
|
|||
+ mode |= RT3883_PCI_MODE_PCI;
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
|
||||
- rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
|
||||
- if (mode & RT3883_PCI_MODE_PCI)
|
||||
- rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
|
||||
+ }
|
||||
+
|
||||
+ if (mode == RT3883_PCI_MODE_NONE) {
|
||||
+ dev_err(dev, "unable to determine PCI mode\n");
|
||||
+ err = -EINVAL;
|
||||
+ goto err_put_hb_node;
|
||||
+ }
|
||||
|
||||
- msleep(500);
|
||||
+
|
||||
+ dev_info(dev, "mode:%s%s\n",
|
||||
+ (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
|
||||
+ (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
|
||||
|
||||
- if (mode & RT3883_PCI_MODE_PCIE) {
|
||||
- err = rt3883_pcie_ready();
|
||||
- if (err)
|
||||
- return;
|
||||
- }
|
||||
+
|
||||
+ rt3883_pci_preinit(rpc, mode);
|
||||
|
||||
- if (mode & RT3883_PCI_MODE_PCI)
|
||||
- rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
|
||||
+
|
||||
+ rpc->pci_controller.pci_ops = &rt3883_pci_ops;
|
||||
+ rpc->pci_controller.io_resource = &rpc->io_res;
|
||||
+ rpc->pci_controller.mem_resource = &rpc->mem_res;
|
||||
|
||||
- rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
|
||||
- rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
|
||||
+
|
||||
+ /* Load PCI I/O and memory resources from DT */
|
||||
+ pci_load_of_ranges(&rpc->pci_controller,
|
||||
+ rpc->pci_controller.of_node);
|
||||
|
@ -682,27 +558,15 @@
|
|||
+
|
||||
+ ioport_resource.start = rpc->io_res.start;
|
||||
+ ioport_resource.end = rpc->io_res.end;
|
||||
|
||||
/* PCI */
|
||||
- rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
|
||||
- rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
|
||||
- rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
|
||||
- rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
|
||||
- rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
|
||||
+
|
||||
+ /* PCI */
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
|
||||
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
|
||||
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
|
||||
+ rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
|
||||
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
|
||||
|
||||
/* PCIe */
|
||||
- rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
|
||||
- rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
|
||||
- rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
|
||||
- rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
|
||||
- rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
|
||||
-
|
||||
- rt3883_pci_irq_init();
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
|
||||
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
|
||||
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
|
||||
|
@ -712,19 +576,13 @@
|
|||
+ err = rt3883_pci_irq_init(dev, rpc);
|
||||
+ if (err)
|
||||
+ goto err_put_hb_node;
|
||||
|
||||
/* PCIe */
|
||||
- val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
|
||||
- val |= 0x7;
|
||||
- rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ /* PCIe */
|
||||
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
|
||||
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
|
||||
|
||||
/* PCI */
|
||||
- val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
|
||||
- val |= 0x7;
|
||||
- rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
|
||||
+
|
||||
+ /* PCI */
|
||||
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
|
||||
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
|
||||
|
@ -745,68 +603,29 @@
|
|||
+ }
|
||||
+
|
||||
+ register_pci_controller(&rpc->pci_controller);
|
||||
|
||||
- ioport_resource.start = rt3883_pci_io_resource.start;
|
||||
- ioport_resource.end = rt3883_pci_io_resource.end;
|
||||
+
|
||||
+ return 0;
|
||||
|
||||
- register_pci_controller(&rt3883_pci_controller);
|
||||
+
|
||||
+err_put_hb_node:
|
||||
+ of_node_put(rpc->pci_controller.of_node);
|
||||
+ return err;
|
||||
}
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
- int irq = -1;
|
||||
-
|
||||
- switch (dev->bus->number) {
|
||||
- case 0:
|
||||
- switch (PCI_SLOT(dev->devfn)) {
|
||||
- case 0x00:
|
||||
- rt3883_pci_wr(0x03ff0001,
|
||||
- RT3883_PCI_REG_BAR0SETUP_ADDR(0));
|
||||
- rt3883_pci_wr(0x03ff0001,
|
||||
- RT3883_PCI_REG_BAR0SETUP_ADDR(1));
|
||||
-
|
||||
- rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
|
||||
- RT3883_MEMORY_BASE);
|
||||
- rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
|
||||
-
|
||||
- irq = RT3883_CPU_IRQ_PCI;
|
||||
- break;
|
||||
- case 0x01:
|
||||
- rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
|
||||
- 0x00000101);
|
||||
- break;
|
||||
- case 0x11:
|
||||
- irq = RT3883_PCI_IRQ_PCI0;
|
||||
- break;
|
||||
- case 0x12:
|
||||
- irq = RT3883_PCI_IRQ_PCI1;
|
||||
- break;
|
||||
- }
|
||||
- break;
|
||||
-
|
||||
- case 1:
|
||||
- irq = RT3883_PCI_IRQ_PCIE;
|
||||
- break;
|
||||
+}
|
||||
+
|
||||
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ struct rt3883_pci_controller *rpc;
|
||||
+ struct of_irq dev_irq;
|
||||
+ int err;
|
||||
+ int irq;
|
||||
|
||||
- default:
|
||||
- dev_err(&dev->dev, "no IRQ specified\n");
|
||||
- return irq;
|
||||
+
|
||||
+ rpc = pci_bus_to_rt3883_controller(dev->bus);
|
||||
+ err = of_irq_map_pci(dev, &dev_irq);
|
||||
+ if (err) {
|
||||
+ pr_err("pci %s: unable to get irq map, err=%d\n",
|
||||
+ pci_name((struct pci_dev *) dev), err);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
+ }
|
||||
+
|
||||
+ irq = irq_create_of_mapping(dev_irq.controller,
|
||||
+ dev_irq.specifier,
|
||||
+ dev_irq.size);
|
||||
|
@ -818,27 +637,20 @@
|
|||
+ pr_info("pci %s: using irq %d for pin %u\n",
|
||||
+ pci_name((struct pci_dev *) dev), irq, pin);
|
||||
+
|
||||
return irq;
|
||||
}
|
||||
|
||||
-void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
|
||||
+ return irq;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
- rt3883_pci_plat_dev_init = f;
|
||||
+{
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
-int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
-{
|
||||
- if (rt3883_pci_plat_dev_init)
|
||||
- return rt3883_pci_plat_dev_init(dev);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rt3883_pci_ids[] = {
|
||||
+ { .compatible = "ralink,rt3883-pci" },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
|
||||
|
||||
- return 0;
|
||||
+
|
||||
+static struct platform_driver rt3883_pci_driver = {
|
||||
+ .probe = rt3883_pci_probe,
|
||||
+ .driver = {
|
||||
|
@ -851,6 +663,16 @@
|
|||
+static int __init rt3883_pci_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&rt3883_pci_driver);
|
||||
}
|
||||
+}
|
||||
+
|
||||
+postcore_initcall(rt3883_pci_init);
|
||||
--- a/arch/mips/ralink/Kconfig
|
||||
+++ b/arch/mips/ralink/Kconfig
|
||||
@@ -20,6 +20,7 @@ choice
|
||||
bool "RT3883"
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
+ select HW_HAS_PCI
|
||||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
|
@ -1,7 +1,7 @@
|
|||
From 1c31c288bc1e853e3226ba593a13a0492b39c9e8 Mon Sep 17 00:00:00 2001
|
||||
From 34fc7d26c01ba594be347aefcc31f55b36c06a72 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Fri, 15 Mar 2013 19:07:05 +0100
|
||||
Subject: [PATCH 120/121] NET: MIPS: add ralink SoC ethernet driver
|
||||
Date: Mon, 22 Apr 2013 23:20:03 +0200
|
||||
Subject: [PATCH 136/137] NET: MIPS: add ralink SoC ethernet driver
|
||||
|
||||
Add support for Ralink FE and ESW.
|
||||
|
||||
|
@ -14,10 +14,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
drivers/net/ethernet/ramips/Kconfig | 18 +
|
||||
drivers/net/ethernet/ramips/Makefile | 9 +
|
||||
drivers/net/ethernet/ramips/ramips_debugfs.c | 127 ++
|
||||
drivers/net/ethernet/ramips/ramips_esw.c | 1220 +++++++++++++++++++
|
||||
drivers/net/ethernet/ramips/ramips_esw.c | 1221 +++++++++++++++++++
|
||||
drivers/net/ethernet/ramips/ramips_eth.h | 375 ++++++
|
||||
drivers/net/ethernet/ramips/ramips_main.c | 1285 ++++++++++++++++++++
|
||||
10 files changed, 3064 insertions(+)
|
||||
drivers/net/ethernet/ramips/ramips_main.c | 1281 ++++++++++++++++++++
|
||||
10 files changed, 3061 insertions(+)
|
||||
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
|
||||
create mode 100644 drivers/net/ethernet/ramips/Kconfig
|
||||
create mode 100644 drivers/net/ethernet/ramips/Makefile
|
||||
|
@ -58,7 +58,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+#endif /* _RT305X_ESW_PLATFORM_H */
|
||||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
|
||||
@@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
|
||||
}
|
||||
|
||||
ralink_clk_add("cpu", cpu_rate);
|
||||
|
@ -1853,7 +1853,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+#endif /* RAMIPS_ETH_H */
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/ethernet/ramips/ramips_main.c
|
||||
@@ -0,0 +1,1285 @@
|
||||
@@ -0,0 +1,1281 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
|
@ -1884,6 +1884,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+#include <linux/of_device.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/of_net.h>
|
||||
+#include <linux/of_mdio.h>
|
||||
+
|
||||
+#include "ramips_eth.h"
|
||||
+
|
||||
|
@ -2262,12 +2263,25 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+static int
|
||||
+ramips_mdio_init(struct raeth_priv *re)
|
||||
+{
|
||||
+ struct device_node *mii_np;
|
||||
+ int err;
|
||||
+ int i;
|
||||
+
|
||||
+ mii_np = of_get_child_by_name(re->of_node, "mdio-bus");
|
||||
+ if (!mii_np) {
|
||||
+ dev_err(re->parent, "no %s child node found", "mdio-bus");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ if (!of_device_is_available(mii_np)) {
|
||||
+ err = 0;
|
||||
+ goto err_put_node;
|
||||
+ }
|
||||
+
|
||||
+ re->mii_bus = mdiobus_alloc();
|
||||
+ if (re->mii_bus == NULL)
|
||||
+ return -ENOMEM;
|
||||
+ if (re->mii_bus == NULL) {
|
||||
+ err = -ENOMEM;
|
||||
+ goto err_put_node;
|
||||
+ }
|
||||
+
|
||||
+ re->mii_bus->name = "ramips_mdio";
|
||||
+ re->mii_bus->read = ramips_mdio_read;
|
||||
|
@ -2278,12 +2292,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+ re->mii_bus->parent = re->parent;
|
||||
+
|
||||
+ snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
|
||||
+ re->mii_bus->phy_mask = 0;
|
||||
+
|
||||
+ for (i = 0; i < PHY_MAX_ADDR; i++)
|
||||
+ re->mii_irq[i] = PHY_POLL;
|
||||
+
|
||||
+ err = mdiobus_register(re->mii_bus);
|
||||
+ err = of_mdiobus_register(re->mii_bus, mii_np);
|
||||
+ if (err)
|
||||
+ goto err_free_bus;
|
||||
+
|
||||
|
@ -2291,13 +2300,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+
|
||||
+err_free_bus:
|
||||
+ kfree(re->mii_bus);
|
||||
+err_put_node:
|
||||
+ of_node_put(mii_np);
|
||||
+ re->mii_bus = NULL;
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+ramips_mdio_cleanup(struct raeth_priv *re)
|
||||
+{
|
||||
+ if (!re->mii_bus)
|
||||
+ return;
|
||||
+
|
||||
+ mdiobus_unregister(re->mii_bus);
|
||||
+ of_node_put(re->mii_bus->dev.of_node);
|
||||
+ kfree(re->mii_bus);
|
||||
+}
|
||||
+
|
||||
|
@ -2330,106 +2346,86 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+}
|
||||
+
|
||||
+static int
|
||||
+ramips_phy_connect_multi(struct raeth_priv *re)
|
||||
+ramips_phy_connect_by_node(struct raeth_priv *re, struct device_node *phy_node)
|
||||
+{
|
||||
+ struct net_device *netdev = re->netdev;
|
||||
+ struct phy_device *phydev = NULL;
|
||||
+ int phy_addr;
|
||||
+ int ret = 0;
|
||||
+ struct phy_device *phydev;
|
||||
+ int phy_mode;
|
||||
+
|
||||
+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
|
||||
+ if (!(re->phy_mask & (1 << phy_addr)))
|
||||
+ continue;
|
||||
+
|
||||
+ if (re->mii_bus->phy_map[phy_addr] == NULL)
|
||||
+ continue;
|
||||
+
|
||||
+ RADEBUG("%s: PHY found at %s, uid=%08x\n",
|
||||
+ netdev->name,
|
||||
+ dev_name(&re->mii_bus->phy_map[phy_addr]->dev),
|
||||
+ re->mii_bus->phy_map[phy_addr]->phy_id);
|
||||
+
|
||||
+ if (phydev == NULL)
|
||||
+ phydev = re->mii_bus->phy_map[phy_addr];
|
||||
+ phy_mode = of_get_phy_mode(re->of_node);
|
||||
+ if (phy_mode < 0) {
|
||||
+ dev_err(re->parent, "incorrect phy-mode\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (!phydev) {
|
||||
+ netdev_err(netdev, "no PHY found with phy_mask=%08x\n",
|
||||
+ re->phy_mask);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev),
|
||||
+ ramips_phy_link_adjust, 0, re->phy_if_mode);
|
||||
+
|
||||
+ if (IS_ERR(re->phy_dev)) {
|
||||
+ netdev_err(netdev, "could not connect to PHY at %s\n",
|
||||
+ dev_name(&phydev->dev));
|
||||
+ phydev = of_phy_connect(re->netdev, phy_node, ramips_phy_link_adjust,
|
||||
+ 0, phy_mode);
|
||||
+ if (IS_ERR(phydev)) {
|
||||
+ dev_err(re->parent, "could not connect to PHY\n");
|
||||
+ return PTR_ERR(re->phy_dev);
|
||||
+ }
|
||||
+
|
||||
+ phydev->supported &= PHY_GBIT_FEATURES;
|
||||
+ phydev->advertising = phydev->supported;
|
||||
+
|
||||
+ RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n",
|
||||
+ netdev->name, dev_name(&phydev->dev),
|
||||
+ phydev->phy_id, phydev->drv->name);
|
||||
+ dev_info(re->parent,
|
||||
+ "connected to PHY at %s [uid=%08x, driver=%s]\n",
|
||||
+ dev_name(&phydev->dev), phydev->phy_id,
|
||||
+ phydev->drv->name);
|
||||
+
|
||||
+ re->phy_dev = phydev;
|
||||
+ re->link = 0;
|
||||
+ re->speed = 0;
|
||||
+ re->duplex = -1;
|
||||
+ re->rx_fc = 0;
|
||||
+ re->tx_fc = 0;
|
||||
+
|
||||
+ return ret;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ramips_phy_connect_fixed(struct raeth_priv *re)
|
||||
+ramips_phy_connect_fixed(struct raeth_priv *re, const __be32 *link, int size)
|
||||
+{
|
||||
+ if (!re->speed) {
|
||||
+ const __be32 *link;
|
||||
+ int size;
|
||||
+
|
||||
+ link = of_get_property(re->of_node,
|
||||
+ "ralink,fixed-link", &size);
|
||||
+ if (!link || size != (4 * sizeof(*link)))
|
||||
+ return -ENOENT;
|
||||
+
|
||||
+ re->speed = be32_to_cpup(link++);
|
||||
+ re->duplex = be32_to_cpup(link++);
|
||||
+ re->tx_fc = be32_to_cpup(link++);
|
||||
+ re->rx_fc = be32_to_cpup(link++);
|
||||
+ if (size != (4 * sizeof(*link))) {
|
||||
+ dev_err(re->parent, "invalid fixed-link property\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ re->speed = be32_to_cpup(link++);
|
||||
+ re->duplex = be32_to_cpup(link++);
|
||||
+ re->tx_fc = be32_to_cpup(link++);
|
||||
+ re->rx_fc = be32_to_cpup(link++);
|
||||
+
|
||||
+ switch (re->speed) {
|
||||
+ case SPEED_10:
|
||||
+ case SPEED_100:
|
||||
+ case SPEED_1000:
|
||||
+ break;
|
||||
+ default:
|
||||
+ netdev_err(re->netdev, "invalid speed specified\n");
|
||||
+ dev_err(re->parent, "invalid link speed: %d\n", re->speed);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ pr_info("%s: using fixed link parameters\n", re->netdev->name);
|
||||
+ dev_info(re->parent, "using fixed link parameters\n");
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ramips_phy_connect(struct raeth_priv *re)
|
||||
+{
|
||||
+ const __be32 *mask;
|
||||
+ struct device_node *phy_node;
|
||||
+ const __be32 *p32;
|
||||
+ int size;
|
||||
+
|
||||
+ mask = of_get_property(re->of_node, "ralink,phy-mask", NULL);
|
||||
+ re->phy_if_mode = of_get_phy_mode(re->of_node);
|
||||
+ phy_node = of_parse_phandle(re->of_node, "phy-handle", 0);
|
||||
+ if (phy_node)
|
||||
+ return ramips_phy_connect_by_node(re, phy_node);
|
||||
+
|
||||
+ if (!re->phy_if_mode || !mask)
|
||||
+ return ramips_phy_connect_fixed(re);
|
||||
+
|
||||
+ re->phy_mask = be32_to_cpup(mask);
|
||||
+ return ramips_phy_connect_multi(re);
|
||||
+ p32 = of_get_property(re->of_node, "ralink,fixed-link", &size);
|
||||
+ if (p32)
|
||||
+ return ramips_phy_connect_fixed(re, p32, size);
|
||||
+
|
||||
+ dev_err(re->parent, "unable to get connection type\n");
|
||||
+ return -EINVAL;
|
||||
+}
|
||||
+
|
||||
+static void
|
|
@ -1,7 +1,7 @@
|
|||
From 8dd2c6ae6d9c858d9c4c4d55aa4bf180669ddfe9 Mon Sep 17 00:00:00 2001
|
||||
From 14c1b064274d28cf88113a685c58374a515f3018 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Tue, 22 Jan 2013 18:23:50 +0100
|
||||
Subject: [PATCH 121/121] watchdog: adds ralink wdt
|
||||
Date: Mon, 22 Apr 2013 23:23:07 +0200
|
||||
Subject: [PATCH 137/137] watchdog: adds ralink wdt
|
||||
|
||||
Adds the watchdog driver for ralink SoC.
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
From 0184f7b64c68fe9606559e86bdd288de01c87a85 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Sun, 17 Mar 2013 10:30:48 +0100
|
||||
Subject: [PATCH 200/208] MIPS: read the mips_machine name from OF and output
|
||||
it in /proc/cpuinfo
|
||||
|
||||
This allows the userland to be compatible to the devive probing of mips_machine.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/prom.h | 3 +++
|
||||
arch/mips/kernel/proc.c | 6 +++++-
|
||||
arch/mips/kernel/prom.c | 24 ++++++++++++++++++++++++
|
||||
3 files changed, 32 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/mips/include/asm/prom.h
|
||||
+++ b/arch/mips/include/asm/prom.h
|
||||
@@ -44,8 +44,11 @@ extern void __dt_setup_arch(struct boot_
|
||||
__dt_setup_arch(&__dtb_##sym##_begin); \
|
||||
})
|
||||
|
||||
+extern char *of_mips_get_machine_name(void);
|
||||
+
|
||||
#else /* CONFIG_OF */
|
||||
static inline void device_tree_init(void) { }
|
||||
+static char *of_mips_get_machine_name(void) { return NULL; }
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
#endif /* __ASM_PROM_H */
|
||||
--- a/arch/mips/kernel/proc.c
|
||||
+++ b/arch/mips/kernel/proc.c
|
||||
@@ -12,6 +12,7 @@
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/processor.h>
|
||||
+#include <asm/prom.h>
|
||||
#include <asm/mips_machine.h>
|
||||
|
||||
unsigned int vced_count, vcei_count;
|
||||
@@ -34,7 +35,10 @@ static int show_cpuinfo(struct seq_file
|
||||
*/
|
||||
if (n == 0) {
|
||||
seq_printf(m, "system type\t\t: %s\n", get_system_type());
|
||||
- if (mips_get_machine_name())
|
||||
+ if (of_mips_get_machine_name())
|
||||
+ seq_printf(m, "machine\t\t\t: %s\n",
|
||||
+ of_mips_get_machine_name());
|
||||
+ else if (mips_get_machine_name())
|
||||
seq_printf(m, "machine\t\t\t: %s\n",
|
||||
mips_get_machine_name());
|
||||
}
|
||||
--- a/arch/mips/kernel/prom.c
|
||||
+++ b/arch/mips/kernel/prom.c
|
||||
@@ -23,6 +23,13 @@
|
||||
#include <asm/page.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
+static char of_mips_machine_name[64] = "Unknown";
|
||||
+
|
||||
+char *of_mips_get_machine_name(void)
|
||||
+{
|
||||
+ return of_mips_machine_name;
|
||||
+}
|
||||
+
|
||||
int __init early_init_dt_scan_memory_arch(unsigned long node,
|
||||
const char *uname, int depth,
|
||||
void *data)
|
||||
@@ -50,6 +57,20 @@ void __init early_init_dt_setup_initrd_a
|
||||
}
|
||||
#endif
|
||||
|
||||
+int __init early_init_dt_scan_model(unsigned long node,
|
||||
+ const char *uname, int depth,
|
||||
+ void *data)
|
||||
+{
|
||||
+ if (!depth) {
|
||||
+ char *model = of_get_flat_dt_prop(node, "model", NULL);
|
||||
+ if (model) {
|
||||
+ snprintf(of_mips_machine_name, sizeof(of_mips_machine_name), model);
|
||||
+ pr_info("MIPS: machine is %s\n", of_mips_machine_name);
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
void __init early_init_devtree(void *params)
|
||||
{
|
||||
/* Setup flat device-tree pointer */
|
||||
@@ -65,6 +86,9 @@ void __init early_init_devtree(void *par
|
||||
/* Scan memory nodes */
|
||||
of_scan_flat_dt(early_init_dt_scan_root, NULL);
|
||||
of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
|
||||
+
|
||||
+ /* try to load the mips machine name */
|
||||
+ of_scan_flat_dt(early_init_dt_scan_model, NULL);
|
||||
}
|
||||
|
||||
void __init __dt_setup_arch(struct boot_param_header *bph)
|
|
@ -34,7 +34,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
--- a/arch/mips/ralink/common.h
|
||||
+++ b/arch/mips/ralink/common.h
|
||||
@@ -46,5 +46,6 @@ extern void prom_soc_init(struct ralink_
|
||||
@@ -51,5 +51,6 @@ extern void prom_soc_init(struct ralink_
|
||||
__iomem void *plat_of_remap_node(const char *node);
|
||||
|
||||
void ralink_pinmux(void);
|
||||
|
@ -43,8 +43,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
#endif /* _RALINK_COMMON_H__ */
|
||||
--- a/arch/mips/ralink/mt7620.c
|
||||
+++ b/arch/mips/ralink/mt7620.c
|
||||
@@ -146,6 +146,11 @@ struct ralink_pinmux rt_pinmux = {
|
||||
// .wdt_reset = rt305x_wdt_reset,
|
||||
@@ -140,6 +140,11 @@ struct ralink_pinmux rt_gpio_pinmux = {
|
||||
.uart_mask = MT7620_GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
+void ralink_usb_platform(void)
|
||||
|
@ -57,7 +57,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
unsigned long cpu_rate, sys_rate;
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -102,6 +102,7 @@ static int __init plat_of_setup(void)
|
||||
@@ -111,6 +111,7 @@ static int __init plat_of_setup(void)
|
||||
panic("failed to populate DT\n");
|
||||
|
||||
ralink_pinmux();
|
||||
|
|
|
@ -32,7 +32,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
+#obj-y += dts/
|
||||
--- a/arch/mips/ralink/of.c
|
||||
+++ b/arch/mips/ralink/of.c
|
||||
@@ -76,6 +76,8 @@ void __init device_tree_init(void)
|
||||
@@ -77,6 +77,8 @@ void __init device_tree_init(void)
|
||||
free_bootmem(base, size);
|
||||
}
|
||||
|
||||
|
@ -41,12 +41,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
|||
void __init plat_mem_setup(void)
|
||||
{
|
||||
set_io_port_base(KSEG1);
|
||||
@@ -84,7 +86,7 @@ void __init plat_mem_setup(void)
|
||||
@@ -85,7 +87,7 @@ void __init plat_mem_setup(void)
|
||||
* Load the builtin devicetree. This causes the chosen node to be
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
- __dt_setup_arch(&__dtb_start);
|
||||
+ __dt_setup_arch(&__image_dtb);
|
||||
}
|
||||
|
||||
static int __init plat_of_setup(void)
|
||||
if (soc_info.mem_size)
|
||||
add_memory_region(soc_info.mem_base, soc_info.mem_size,
|
||||
|
|
|
@ -1,176 +0,0 @@
|
|||
From bcd97dbdcb7bc0300397db481872252e8849307b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <blogic@openwrt.org>
|
||||
Date: Mon, 25 Mar 2013 10:50:53 +0100
|
||||
Subject: [PATCH 207/208] owrt: MIPS: ralink: add support for runtime memory
|
||||
detection
|
||||
|
||||
This allows us to add a device_node called "memorydetect" to the DT with
|
||||
information about the memory windoe of the SoC. Based on this the memory is
|
||||
detected ar runtime.
|
||||
|
||||
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
---
|
||||
arch/mips/include/asm/prom.h | 3 ++
|
||||
arch/mips/kernel/prom.c | 3 ++
|
||||
arch/mips/ralink/Makefile | 2 +-
|
||||
arch/mips/ralink/memory.c | 119 ++++++++++++++++++++++++++++++++++++++++++
|
||||
4 files changed, 126 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/mips/ralink/memory.c
|
||||
|
||||
--- a/arch/mips/include/asm/prom.h
|
||||
+++ b/arch/mips/include/asm/prom.h
|
||||
@@ -20,6 +20,9 @@
|
||||
extern int early_init_dt_scan_memory_arch(unsigned long node,
|
||||
const char *uname, int depth, void *data);
|
||||
|
||||
+extern int early_init_dt_detect_memory(unsigned long node,
|
||||
+ const char *uname, int depth, void *data);
|
||||
+
|
||||
extern void device_tree_init(void);
|
||||
|
||||
static inline unsigned long pci_address_to_pio(phys_addr_t address)
|
||||
--- a/arch/mips/kernel/prom.c
|
||||
+++ b/arch/mips/kernel/prom.c
|
||||
@@ -88,6 +88,9 @@ void __init early_init_devtree(void *par
|
||||
of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
|
||||
|
||||
/* try to load the mips machine name */
|
||||
+ of_scan_flat_dt(early_init_dt_detect_memory, NULL);
|
||||
+
|
||||
+ /* try to load the mips machine name */
|
||||
of_scan_flat_dt(early_init_dt_scan_model, NULL);
|
||||
}
|
||||
|
||||
--- a/arch/mips/ralink/Makefile
|
||||
+++ b/arch/mips/ralink/Makefile
|
||||
@@ -6,7 +6,7 @@
|
||||
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
|
||||
-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
|
||||
+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o memory.o
|
||||
|
||||
obj-$(CONFIG_SOC_RT288X) += rt288x.o
|
||||
obj-$(CONFIG_SOC_RT305X) += rt305x.o rt305x-usb.o
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ralink/memory.c
|
||||
@@ -0,0 +1,119 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License version 2 as published
|
||||
+ * by the Free Software Foundation.
|
||||
+ *
|
||||
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/string.h>
|
||||
+#include <linux/of_fdt.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+
|
||||
+#include <asm/bootinfo.h>
|
||||
+#include <asm/addrspace.h>
|
||||
+
|
||||
+#include "common.h"
|
||||
+
|
||||
+#define MB (1024 * 1024)
|
||||
+
|
||||
+unsigned long ramips_mem_base;
|
||||
+unsigned long ramips_mem_size_min;
|
||||
+unsigned long ramips_mem_size_max;
|
||||
+
|
||||
+#ifdef CONFIG_SOC_RT305X
|
||||
+
|
||||
+#include <asm/mach-ralink/rt305x.h>
|
||||
+
|
||||
+static unsigned long rt5350_get_mem_size(void)
|
||||
+{
|
||||
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
|
||||
+ unsigned long ret;
|
||||
+ u32 t;
|
||||
+
|
||||
+ t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
|
||||
+ t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
|
||||
+ RT5350_SYSCFG0_DRAM_SIZE_MASK;
|
||||
+
|
||||
+ switch (t) {
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_2M:
|
||||
+ ret = 2 * 1024 * 1024;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_8M:
|
||||
+ ret = 8 * 1024 * 1024;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_16M:
|
||||
+ ret = 16 * 1024 * 1024;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_32M:
|
||||
+ ret = 32 * 1024 * 1024;
|
||||
+ break;
|
||||
+ case RT5350_SYSCFG0_DRAM_SIZE_64M:
|
||||
+ ret = 64 * 1024 * 1024;
|
||||
+ break;
|
||||
+ default:
|
||||
+ panic("rt5350: invalid DRAM size: %u", t);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
+static void __init detect_mem_size(void)
|
||||
+{
|
||||
+ unsigned long size;
|
||||
+
|
||||
+#ifdef CONFIG_SOC_RT305X
|
||||
+ if (soc_is_rt5350()) {
|
||||
+ size = rt5350_get_mem_size();
|
||||
+ } else
|
||||
+#endif
|
||||
+ {
|
||||
+ void *base;
|
||||
+
|
||||
+ base = (void *) KSEG1ADDR(detect_mem_size);
|
||||
+ for (size = ramips_mem_size_min; size < ramips_mem_size_max;
|
||||
+ size <<= 1 ) {
|
||||
+ if (!memcmp(base, base + size, 1024))
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ pr_info("memory detected: %uMB\n", (unsigned int) size / MB);
|
||||
+
|
||||
+ add_memory_region(ramips_mem_base, size, BOOT_MEM_RAM);
|
||||
+}
|
||||
+
|
||||
+int __init early_init_dt_detect_memory(unsigned long node, const char *uname,
|
||||
+ int depth, void *data)
|
||||
+{
|
||||
+ unsigned long l;
|
||||
+ __be32 *mem;
|
||||
+
|
||||
+ /* We are scanning "memorydetect" nodes only */
|
||||
+ if (depth != 1 || strcmp(uname, "memorydetect") != 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ mem = of_get_flat_dt_prop(node, "ralink,memory", &l);
|
||||
+ if (mem == NULL)
|
||||
+ return 0;
|
||||
+
|
||||
+ if ((l / sizeof(__be32)) != 3)
|
||||
+ panic("invalid memorydetect node\n");
|
||||
+
|
||||
+ ramips_mem_base = dt_mem_next_cell(dt_root_addr_cells, &mem);
|
||||
+ ramips_mem_size_min = dt_mem_next_cell(dt_root_size_cells, &mem);
|
||||
+ ramips_mem_size_max = dt_mem_next_cell(dt_root_size_cells, &mem);
|
||||
+
|
||||
+ pr_info("memory window: 0x%llx, min: %uMB, max: %uMB\n",
|
||||
+ (unsigned long long) ramips_mem_base,
|
||||
+ (unsigned int) ramips_mem_size_min / MB,
|
||||
+ (unsigned int) ramips_mem_size_max / MB);
|
||||
+
|
||||
+ detect_mem_size();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
|
@ -1,14 +0,0 @@
|
|||
--- a/arch/mips/ralink/rt305x.c
|
||||
+++ b/arch/mips/ralink/rt305x.c
|
||||
@@ -97,6 +97,11 @@ struct ralink_pinmux_grp uart_mux[] = {
|
||||
.mask = RT305X_GPIO_MODE_GPIO_I2S,
|
||||
.gpio_first = RT305X_GPIO_7,
|
||||
.gpio_last = RT305X_GPIO_14,
|
||||
+ }, {
|
||||
+ .name = "gpio",
|
||||
+ .mask = RT305X_GPIO_MODE_GPIO,
|
||||
+ .gpio_first = RT305X_GPIO_7,
|
||||
+ .gpio_last = RT305X_GPIO_14,
|
||||
}, {0}
|
||||
};
|
||||
|
Loading…
Reference in a new issue