2016-09-08 22:57:31 +00:00
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/dts-v1/;
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2016-11-11 06:32:12 +00:00
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#include "mt7628an.dtsi"
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2016-09-08 22:57:31 +00:00
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2017-07-29 02:14:07 +00:00
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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2016-09-08 22:57:31 +00:00
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/ {
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2017-07-29 02:14:07 +00:00
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compatible = "mercury,mac1200r-v2", "mediatek,mt7628an-soc";
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2016-09-08 22:57:31 +00:00
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model = "Mercury MAC1200R v2";
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2018-07-16 08:27:22 +00:00
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aliases {
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2018-08-28 04:54:27 +00:00
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led-boot = &led_status;
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led-failsafe = &led_status;
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led-running = &led_status;
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led-upgrade = &led_status;
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2018-07-16 08:27:22 +00:00
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};
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2016-09-08 22:57:31 +00:00
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x2000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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2018-07-16 08:27:22 +00:00
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led_status: status {
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2016-09-08 22:57:31 +00:00
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label = "mac1200rv2:green:status";
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2017-07-29 02:14:07 +00:00
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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2016-09-08 22:57:31 +00:00
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};
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};
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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2017-02-02 21:11:23 +00:00
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compatible = "jedec,spi-nor";
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2016-09-08 22:57:31 +00:00
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reg = <0 0>;
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spi-max-frequency = <10000000>;
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m25p,chunked-io = <32>;
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2018-08-01 20:32:34 +00:00
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x1d800>;
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};
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factory: partition@1d800 {
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label = "factory_info";
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reg = <0x1d800 0x800>;
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read-only;
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};
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art: partition@1e000 {
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label = "art";
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reg = <0x1e000 0x2000>;
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read-only;
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};
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partition@20000 {
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label = "config";
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reg = <0x20000 0x10000>;
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};
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partition@30000 {
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label = "u-boot2";
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reg = <0x30000 0x10000>;
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};
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partition@40000 {
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2018-11-28 03:28:35 +00:00
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compatible = "denx,uimage";
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2018-08-01 20:32:34 +00:00
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label = "firmware";
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reg = <0x40000 0x7c0000>;
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};
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2016-09-08 22:57:31 +00:00
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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mtd-mac-address = <&factory 0xd>;
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2017-02-14 13:08:59 +00:00
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mediatek,portmap = "llllw";
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2016-09-08 22:57:31 +00:00
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};
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&wmac {
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status = "okay";
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ralink,mtd-eeprom = <&art 0x0>;
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};
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&pcie {
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status = "okay";
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2018-07-21 14:19:46 +00:00
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&art 0x1000>;
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ieee80211-freq-limit = <5000000 6000000>;
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2016-09-08 22:57:31 +00:00
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};
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};
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