155 lines
5.1 KiB
Diff
155 lines
5.1 KiB
Diff
--- a/arch/mips/bcm947xx/include/sbchipc.h 2007-11-23 12:12:01.000000000 -0500
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+++ b/arch/mips/bcm947xx/include/sbchipc.h 2007-11-25 06:16:42.000000000 -0500
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@@ -188,6 +188,7 @@
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#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CAP_ROM 0x00800000 /* Internal boot rom active */
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#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
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+#define CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
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/* PLL type */
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#define PLL_NONE 0x00000000
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@@ -199,6 +200,9 @@
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#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
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#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
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+/* watchdog clock */
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+#define WATCHDOG_CLOCK_5354 32000 /* Hz */
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+
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/* corecontrol */
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#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
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#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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--- a/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-23 12:12:01.000000000 -0500
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+++ b/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-25 05:58:20.000000000 -0500
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@@ -121,6 +121,7 @@
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#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
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#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
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#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
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+#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
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#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
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--- a/arch/mips/bcm947xx/sbmips.c 2007-11-23 12:12:02.000000000 -0500
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+++ b/arch/mips/bcm947xx/sbmips.c 2007-11-25 05:40:40.000000000 -0500
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@@ -290,6 +290,12 @@
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n = R_REG(osh, &eir->clockcontrol_n);
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m = R_REG(osh, &eir->clockcontrol_sb);
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} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
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+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
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+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
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+ rate = 240000000;
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+ goto out;
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+ }
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+
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pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
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n = R_REG(osh, &cc->clockcontrol_n);
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if ((pll_type == PLL_TYPE2) ||
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@@ -612,6 +618,15 @@
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clockcontrol_pci = &eir->clockcontrol_pci;
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clockcontrol_m2 = &cc->clockcontrol_m2;
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} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
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+
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+ /* 5354 chipcommon pll setting can't be changed.
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+ * The PMU on power up comes up with the default clk frequency
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+ * of 240MHz
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+ */
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+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
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+ ret = TRUE;
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+ goto done;
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+ }
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pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
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if (pll_type == PLL_TYPE6) {
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clockcontrol_n = NULL;
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--- a/arch/mips/bcm947xx/sbutils.c 2007-11-23 12:12:02.000000000 -0500
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+++ b/arch/mips/bcm947xx/sbutils.c 2007-11-25 06:22:43.000000000 -0500
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@@ -791,8 +791,14 @@
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/* readback */
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if (regoff >= SBCONFIGOFF)
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w = R_SBREG(si, r);
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- else
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+ else {
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+ if ((si->sb.chip == BCM5354_CHIP_ID) &&
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+ (coreidx == SB_CC_IDX) &&
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+ (regoff == OFFSETOF(chipcregs_t, watchdog))) {
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+ w = val;
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+ } else
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w = R_REG(si->osh, r);
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+ }
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if (!fast) {
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/* restore core index */
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@@ -1902,6 +1908,15 @@
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n = R_REG(si->osh, &eir->clockcontrol_n);
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m = R_REG(si->osh, &eir->clockcontrol_sb);
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} else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
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+
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+ if (R_REG(si->osh, &cc->capabilities) & CAP_PMU) {
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+ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
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+ /* 5354 has a constant sb clock of 120MHz */
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+ rate = 120000000;
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+ goto end;
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+ } else
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+ ASSERT(0);
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+ }
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pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
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if (pll_type == PLL_NONE) {
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INTR_RESTORE(si, intr_val);
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@@ -1929,6 +1944,7 @@
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rate = rate / 2;
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}
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+end:
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/* switch back to previous core */
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sb_setcoreidx(sbh, idx);
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--- a/arch/mips/bcm947xx/hndchipc.c 2007-11-23 12:12:02.000000000 -0500
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+++ b/arch/mips/bcm947xx/hndchipc.c 2007-11-25 06:31:15.000000000 -0500
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@@ -93,6 +93,9 @@
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chipcregs_t *cc = (chipcregs_t *) regs;
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uint32 rev, cap, pll, baud_base, div;
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+ /* Default value */
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+ div = 48;
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+
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/* Determine core revision and capabilities */
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rev = sb_corerev(sbh);
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cap = R_REG(osh, &cc->capabilities);
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@@ -108,22 +111,29 @@
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R_REG(osh, &cc->clockcontrol_m2));
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div = 1;
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} else {
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- /* Fixed ALP clock */
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- if (rev >= 11 && rev != 15) {
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- baud_base = 20000000;
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+/* 5354 chip common uart uses a constant clock
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+ * frequency of 25MHz */
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+ if (sb_corerev(sbh) == 20) {
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+ /* Set the override bit so we don't divide it */
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+ W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
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+ baud_base = 25000000;
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+ } else if (rev >= 11 && rev != 15) {
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+ /* Fixed ALP clock */
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+// baud_base = sb_alp_clock(sbh);
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+ baud_base = 20000000;
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div = 1;
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/* Set the override bit so we don't divide it */
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W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
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- }
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+
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/* Internal backplane clock */
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- else if (rev >= 3) {
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- baud_base = sb_clock(sbh);
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- div = 2; /* Minimum divisor */
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- W_REG(osh, &cc->clkdiv,
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+ } else if (rev >= 3) {
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+ baud_base = sb_clock(sbh);
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+ div = 2; /* Minimum divisor */
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+ W_REG(osh, &cc->clkdiv,
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((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
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- }
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+
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/* Fixed internal backplane clock */
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- else {
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+ } else {
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baud_base = 88000000;
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div = 48;
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}
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