429 lines
8.8 KiB
Text
429 lines
8.8 KiB
Text
/*
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* Copyright 2013 Gateworks Corporation
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6q-ventana.dtsi"
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/ {
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model = "Gateworks Ventana GW5400-A";
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compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
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aliases {
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ethernet0 = &fec;
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ethernet1 = ð1;
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sky2 = ð1;
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};
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/* SDRAM addressing */
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memory {
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reg = <0x10000000 0x40000000>;
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};
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chosen {
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bootargs = "console=ttymxc1,115200";
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};
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leds {
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compatible = "gpio-leds";
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led0: user0 {
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label = "user0";
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gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG# */
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linux,default-trigger = "heartbeat";
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};
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led1: user1 {
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label = "user1";
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gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR# */
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};
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led2: user2 {
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label = "user2";
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gpios = <&gpio4 15 0>; /* 111 -> MX6_LOCLEDR# */
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};
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};
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regulators {
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compatible = "simple-bus";
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reg_2p5v: 2p5v {
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compatible = "regulator-fixed";
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regulator-name = "2P5V";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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reg_3p3v: 3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb_otg_vbus: usb_otg_vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 0>;
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enable-active-high;
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};
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};
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sound {
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compatible = "fsl,imx6q-sabrelite-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx6q-sabrelite-sgtl5000";
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ssi-controller = <&ssi1>;
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audio-codec = <&codec>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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mux-int-port = <1>;
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mux-ext-port = <4>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* USB OTG Power Enable */
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MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
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/* 3:19 SPINOR_CS0# */
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MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
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/* 1:09 MX6_DIO0 (could also be PWM1_PWM0) */
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MX6Q_PAD_GPIO_9__GPIO1_IO09 0x80000000
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/* 1:19 MX6_DIO1 (could also be PWM2_PWM0) */
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MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
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/* 2:09 MX6_DIO2 (could also be PWM3_PWM0) */
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MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
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/* 2:10 MX6_DIO3 (could also be PWM3_PWM0) */
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MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x80000000
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/* 1:16 USBHUB_RST# */
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MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
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/* PCIE IRQ */
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MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
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/* PCIE RST */
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MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x08000000
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/* 1:12 MIPI_DIO */
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MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000
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/* AUD4_MCK */
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MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
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>;
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};
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};
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#if 0
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/* ipu1: IPU1_CSI0: HDMI reciver (Digital Video In) */
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ipu1 {
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pinctrl_ipu1_1: ipu1grp-5 {
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fsl,pins = <
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MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC
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MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN
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MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK
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MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC
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MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04
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MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05
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MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06
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MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07
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MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08
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MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09
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MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10
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MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11
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MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12
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MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13
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MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14
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MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15
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MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16
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MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17
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MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18
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MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19
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>;
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};
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};
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/* ipu2: IPU1_CSI1: Analog Video Decoder (Analog Video In) */
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/* IPU2_CSI1: Analog Video Decoder (Analog Video In) */
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ipu2 {
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pinctrl_ipu2_1: ipu2grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12
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MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13
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MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14
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MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15
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MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16
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MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17
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MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18
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MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19
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MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC
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MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC
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// not sure why this causes kernel to crash in early init
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// MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK
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>;
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};
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};
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/* ipu3: IPU2_DISP0: Analog Video Encoder (Analog Video Out) */
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ipu3 {
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pinctrl_ipu3_1: ipu3grp-5 {
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fsl,pins = <
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MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00
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MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01
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MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02
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MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03
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MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04
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MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05
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MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06
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MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07
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MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08
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MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09
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MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10
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MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11
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MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12
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MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13
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MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14
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MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15
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>;
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};
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};
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#endif
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1>;
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status = "okay";
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sst,w25q256";
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spi-max-frequency = <30000000>;
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reg = <0>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_2>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_1>;
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status = "okay";
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};
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&uart5 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5_1>;
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};
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&ssi1 {
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fsl,mode = "i2s-slave";
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status = "okay";
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};
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&ssi2 {
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fsl,mode = "i2s-slave";
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status = "okay";
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};
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&can1 {
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reg = <0x02090000 0x4000>;
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interrupts = <0 110 0x04>;
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//clock-frequency
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status = "okay";
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};
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&usbh1 {
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status = "okay";
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};
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&pcie {
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rst-gpios = <&gpio1 29 0>; /* PCIESWT_RST# */
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clken-gpios = <&gpio1 20 0>; /* not used */
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status = "okay";
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eth1: sky2@8 { /* MAC/PHY on bus 8 */
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compatible = "marvell,sky2";
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/* Filled in by U-Boot */
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mac-address = [ 00 00 00 00 00 00 ];
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_1>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio1 30 0>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3_2>;
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cd-gpios = <&gpio7 0 0>;
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vmmc-supply = <®_3p3v>;
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status = "okay";
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux_3>;
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_1>;
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eeprom: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom1: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom2: eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom3: eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom4: eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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rtc: ds1672@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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gpio: pca9555@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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hwmon: gsc@29 {
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compatible = "gw,gsp";
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reg = <0x29>;
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};
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};
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&i2c2 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_2>;
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pmic: pfuze@08 {
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compatible = "fsl,pfuze100";
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reg = <0x0a>;
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};
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pciswitch: pex8609@3f {
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compatible = "plx,pex8609";
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reg = <0x3f>;
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};
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pciclkgen: si52147@6b {
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compatible = "sil,si52147";
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reg = <0x6b>;
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};
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};
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&i2c3 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_2>;
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks 169>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_3p3v>;
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};
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accelerometer: mma8450@1c {
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compatible = "fsl,mma8450";
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reg = <0x1c>;
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};
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videoout: adv7393@2a {
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compatible = "adi,adv7393";
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reg = <0x2a>;
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};
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videoin: adv7180@20 {
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compatible = "adi,adv7180";
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reg = <0x20>;
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};
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hdmiin: adv7611@4c {
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compatible = "adi,adv7611";
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reg = <0x4c>;
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};
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touchscreen: egalax_ts@04 {
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compatible = "eeti,egalax_ts";
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reg = <0x04>;
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wakeup-gpios = <&gpio1 12 0>;
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};
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};
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&ldb {
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status = "okay";
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lvds-channel@0 {
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crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
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};
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};
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