15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
From 9722009432a5553b11c8e0a04a275654de11dbc4 Mon Sep 17 00:00:00 2001
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From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
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Date: Mon, 13 Jun 2016 16:33:06 +0530
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Subject: [PATCH 53/93] armv8: arch-fsl-layerscape: Update name of Soc
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Update the name of the Soc.
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Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
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---
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arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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index e4ff990..7a943be 100644
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--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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@@ -8,13 +8,13 @@
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#define _FSL_LAYERSCAPE_CPU_H
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static struct cpu_type cpu_type_list[] = {
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- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
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- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
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- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
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- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
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- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
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- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
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- CPU_TYPE_ENTRY(LS1012, LS1012, 1),
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+ CPU_TYPE_ENTRY(LS2080A, LS2080, 8),
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+ CPU_TYPE_ENTRY(LS2085A, LS2085, 8),
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+ CPU_TYPE_ENTRY(LS2045A, LS2045, 4),
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+ CPU_TYPE_ENTRY(LS1043A, LS1043, 4),
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+ CPU_TYPE_ENTRY(LS1023A, LS1023, 2),
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+ CPU_TYPE_ENTRY(LS2040A, LS2040, 4),
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+ CPU_TYPE_ENTRY(LS1012A, LS1012, 1),
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};
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#ifndef CONFIG_SYS_DCACHE_OFF
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--
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1.7.9.5
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