e07c4f2150
Some Lantiq SoCs are not able to use buffered writes properly with Intel command set flash due to the way NOR addresses on EBU are manipulated. This patch disables buffered writes on those devices. The only device affected at the moment is ARV4510PW, others use AMD/Fujitsu command set. Signed-off-by: Matti Laakso <malaakso@elisanet.fi> SVN-Revision: 44451
11 lines
309 B
Diff
11 lines
309 B
Diff
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
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@@ -40,7 +40,7 @@
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/* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
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// debugging, turns off buffer write mode if set to 1
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-#define FORCE_WORD_WRITE 0
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+#define FORCE_WORD_WRITE 1
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/* Intel chips */
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#define I82802AB 0x00ad
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