2c05915b24
L2 cache via L2X0 cache controller available on some ARM boards can provide a performance boost in some situations but decrease performance in others. This adds a kernel cmdline to disable L2X0 for cns3xxx based boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 34874
47 lines
1.1 KiB
Diff
47 lines
1.1 KiB
Diff
--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -284,11 +284,24 @@ struct sys_timer cns3xxx_timer = {
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#ifdef CONFIG_CACHE_L2X0
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+static int cns3xxx_l2x0_enable = 1;
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+
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+static int __init cns3xxx_l2x0_disable(char *s)
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+{
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+ cns3xxx_l2x0_enable = 0;
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+ return 1;
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+}
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+__setup("nol2x0", cns3xxx_l2x0_disable);
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+
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void __init cns3xxx_l2x0_init(void)
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{
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- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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+ void __iomem *base;
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u32 val;
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+ if (!cns3xxx_l2x0_enable)
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+ return;
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+
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+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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if (WARN_ON(!base))
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return;
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@@ -321,6 +334,7 @@ void __init cns3xxx_l2x0_init(void)
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/* 32 KiB, 8-way, parity disable */
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l2x0_init(base, 0x00540000, 0xfe000fff);
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}
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+arch_initcall(cns3xxx_l2x0_init);
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#endif /* CONFIG_CACHE_L2X0 */
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -193,8 +193,6 @@ static struct platform_device *cns3420_p
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static void __init cns3420_init(void)
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{
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- cns3xxx_l2x0_init();
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-
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platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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cns3xxx_ahci_init();
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