oneshot and timer have the same configuration options, just a different
trigger name.
Signed-off-by: Karl Palsson <karlp@etactica.com>
SVN-Revision: 48770
- remove the suffix (N, ND) to indicate that the image is for all
WR841-models
- some of these models have a "N"-suffix, others have (ND)-suffix,
but the boards are the same - only difference is the detachable
antenna on "D"-models
- discussed this idea to remove the suffix in IRC with jow and Borromini
Signed-off-by: Sven Roederer <devel-sven@geroedel.de>
SVN-Revision: 48767
Before r47933 Bit 1 (first bit) of xTSE Octet 1 (first octet) defaulted
to 1, which allowed T1.413 to operate.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
SVN-Revision: 48763
Seama format has 2 similar headers: container (seal) header and entity
header. The first one has size always set to 0 and doesn't contain MD5
digest.
When dealing with Seama on a flash we deal directly with an entity. You
can see mtdsplit_parse_seama reads from offset 0 and expects entity to
be there. Seama container is used by bootloader / interface only which
extract entity out of it and flash it.
That said we should fix our header struct. This is important as we
calculate possible rootfs offset assuming it may be placed right after
Seama entity. So far calculate offset was always 16B too low.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48754
- Fix typo in board_data partition start address
- Increase board_data partition size in order to exploit all flash size
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
SVN-Revision: 48751
This adds option to build kernel module and firmware packages
for a Marvell 8686 SPI Wireless device
Signed-off-by: Joseph Honold <mozzwald@gmail.com>
SVN-Revision: 48750
This patch introduces support of new boards with ARC HS38 cores.
ARC HS38 is a new generation of ARC cores which utilize ARCv2 ISA.
As with ARC770 we're addind support for 2 boards for now:
[1] Synopsys SDP board (AXS103)
This is the same base-board as in AXS101 but with
FPGA-based CPU-tile where ARCHs38 core is implemented.
[2] nSIM
Again this is the same simulation engine but configured for
new instruction set and features of new CPU.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 48740
This change adds support of ARC ISAv2 processors in
OpenWRT toolchain.
In general gcc for ARC may compile code for both ISA versions
simultaneously but libgcc will be built only for default
architecture that's why it's necessary to specify --with-cpu
on gcc configuration.
As for uClibc we need to use different configurations for
different ARC ISAs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 48739
Refresh patches and rework Makefile to fetch glibc from release branches
instead of relying on tarballs.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 48735
Changeset r48416 broke the downloading of mirrored, packed scm checkouts.
Fix this by removing the "@" sign in front of the download command which is
now executed as part of a larger shell command under flock.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 48733
This patch adds support for Phicomm PSG1208.This is a router with MT7620A SoC with 8M flash and 64M ram.
The WPS led is uesd as status_led because the power light can't be controlled with GPIO.
It seems that the 5g wifi led is connected to MT7612E and it can't be controlled with GPIO too.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
SVN-Revision: 48721
