This patch improves the default configuration of DWC2 on lantiq SoCs
somewhat:
* Set maximum packet count to largest allowed value by the DWC2 (511)
* Use 16-bit DMA bursts
* Divide fifo buffers more evenly
Default fifo buffer sizes from original ltq-hcd driver seem really
irrational. For example according to DWC2 data book rxfifo size of 240
will not fit even a single full length USB packet. On the other hand
non-periodic tx fifo size of 240 is more than enough to fit one complete
packet.
Change the sizes around to improve the situation and to fix some issues
especially with isochronous USB transfers.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
SVN-Revision: 47563
Add AR9 DTS definition to be recognized by the DWC2 driver.
The same driver parameters can be mostly used except that some boards
seem to erroneously report OTG HNP/SRP capability of the USB HCD.
Forcing the HNP/SRP off allows these boards to work with the DWC2 as well.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
SVN-Revision: 46915
Lantiq driver does not work with autodetected fifo sizes so use ones
from original ltq-hcd driver in dwc2. Other values can be
autodetected.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
SVN-Revision: 44674
