Wallys DR531 is based on Qualcomm Atheros QCA9531 v2.
Short specification:
- 550/400/200 MHz (CPU/DDR/AHB)
- 2x 10/100 Mbps Ethernet
- 64 MB of RAM (DDR2)
- 8 MB of FLASH
- 2T2R 2.4 GHz with external PA (SE2576L), up to 30 dBm
- 2x MMCX connectors
- mini-PCIe connector with PCIe/USB buses and SIM slot
- 7x LED, 1x button, 1x optional buzzer
- UART, (E)JTAG and LED headers
Default configuration:
- WAN on eth1 (RJ45 near DC jack)
- LAN on eth0 (RJ45 near button)
- S4 LED set to be status LED
- all LEDs configurable form user space
- button configured for reset
Flash instruction (do it under U-Boot, using UART):
1. tftp 0x80060000 lede-ar71xx-generic-dr531-squashfs-sysupgrade.bin
2. erase 0x9f050000 +$filesize
3. cp.b $fileaddr 0x9f050000 $filesize
4. setenv bootcmd "bootm 0x9f050000"
5. saveenv && reset
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
In new kernels we should use clk_prepare_enable instead of clk_enable
since clk_enable does not make proper initialization that leads
to rise WARN_ON messages and not working spi bus on the device.
Signed-off-by: Sergey Sergeev <adron@yapic.net>
Should fix LAN speed issues on some devices. This is an updated version
of the previously reverted commit with the same name.
It improves the check for MACs connected to a built-in switch
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This patch adds the target profile SOM9331 and configures hardware
functionality for the 3x Eth Ports & corresponding LED's, the USB Host,
the USART to USB bridge and the System LED.
Signed-off-by: Allan Nick Pedrana <nik9993@gmail.com>
The cpe510 has two calibration tables. The first calibration
table requires to modify ath9k driver to work (patched tx gain table).
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The LNA improves the rx path. Within a simple test setup
it improved the signal from -60dbm to -40dbm.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
- CPU QCA9531-BL3A
- RAM: 64MB
- flash: 16MB
- USB
AP143 platform, similar to tl-wr841n v10/v11, but with USB
Signed-off-by: Cezary Jackiewicz <cezary@eko.one.pl>
To avoid confusion with different unifiac devices, rename existing target
"unifiac" to "unifiac-lite", before "unifiac-pro" is introduced.
Signed-off-by: P.Wassi <p.wassi at gmx.at>
The file linux/mdio-gpio.h was moved to linux/platform_data/mdio-gpio.h
in kernel 4.4
Reported-by: Arjen de Korte <arjen+openwrt@de-korte.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 49193
OpenWrt can be flashed with following uboot commands:
tftpboot 0x80500000 openwrt-ar71xx-generic-wpj342-16M-squashfs-sysupgrade.bin
erase 0x9f030000 +$filesize
cp.b $fileaddr 0x9f030000 $filesize
Signed-off-by: Christian Mehlis <christian@m3hlis.de>
SVN-Revision: 49157
This patch provides full GPIO support for WNR2200 (LEDs and buttons).
It exposes all LEDs to operating system, including Ethernet ones.
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
SVN-Revision: 49101
Fix for invalid/random/duplicate WLAN MAC address in WNR2200.
Permanent platform MAC is calculated and assigned during system startup.
WLAN MAC follows wired Ethernet interface addresses.
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
SVN-Revision: 49100
This patch provides full GPIO support for WNR1000v2 (LEDs and buttons).
It exposes all LEDs to operating system, including Ethernet ones.
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
SVN-Revision: 49076
Not all mach-* files set all boards correctly in ETH_CFG. They depend on
some preset values by u-boot which were not previously modified by
ath79_setup_qca955x_eth_cfg. Avoiding to modify them in this function keeps
it backward compatible for these boards.
This reverts commit 119b8ab2c2eac237ec4e9c4d0ed53df22b5c6978.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49072
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.
This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49071
The MR1750 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR1750 can be used instead.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49070
The MR900 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR900 can be used instead.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49069
Fix for invalid/random WLAN MAC address in WNR1000v2. Permanent platform
MAC is calculated and assigned during system startup. WLAN MAC follows
wired Ethernet interface addresses. This is the same fix as for WNR2000v3
and WNR612v2.
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
SVN-Revision: 49051
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49031
The delays of PHY/MAC on the MR900 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49030
