Commit graph

18 commits

Author SHA1 Message Date
Chuanhong Guo
028daa9974 ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.

This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)

Introduced "qca,mac-idx" for the difference in MII_CTRL register value.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-08-28 11:26:53 +02:00
Christian Lamparter
f3ffac90bc ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
Some AR9344 boards do very poorly with the default settings and
need custom rxdv-delay, rxd-delay, txd-delay, txen-delay flags
to perform reasonably.

In this case the WD My Net Wi-Fi Range Extender can not even
manage 10Mbps on a 1Gbit link:

root@AR9344:~# iperf3 -s
-----------------------------------------------------------
Server listening on 5201
-----------------------------------------------------------
Accepted connection from client [...]
[  5] local [...] connected to client
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  1.09 MBytes  9.16 Mbits/sec
[  5]   1.00-2.00   sec   895 KBytes  7.33 Mbits/sec
[  5]   2.00-3.00   sec   762 KBytes  6.25 Mbits/sec
[...]
[  5]  10.00-10.03  sec  17.0 KBytes  4.74 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.03  sec  9.00 MBytes  7.52 Mbits/sec

with but with the correct settings in place, it does much better:

root@AR9344:~# iperf3 -s
-----------------------------------------------------------
Server listening on 5201
-----------------------------------------------------------
Accepted connection from client [...]
[  5] local [...] connected to client
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  23.1 MBytes   193 Mbits/sec
[  5]   1.00-2.00   sec  23.1 MBytes   194 Mbits/sec
[  5]   2.00-3.00   sec  23.2 MBytes   195 Mbits/sec
[...]
[  5]  10.00-10.04  sec   710 KBytes   180 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.04  sec   237 MBytes   198 Mbits/sec

The tx data and enable delay bits definitions are taken from Atheros'
AR9344 Data Sheet Section "8.6.1 Ethernet Configuration (ETH_CFG)" on
page 153.

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2018-08-13 08:48:37 +02:00
David Bauer
7d1b742b4d ath79: add QCA956x GMAC config
This commit adds the ability to configure the GMAC of the QCA956x.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-08-13 08:43:15 +02:00
Chuanhong Guo
42b3fdf981 ath79: ag71xx: fix speed applied to MII0/1_CTRL on ar71xx/ar913x
Currently speed value is applied to interface mode field.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-08-13 08:37:19 +02:00
Chuanhong Guo
387736af41 ath79: ag71xx: remove PHY reset
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET
in datasheets will trigger either a reset for builtin switch or assert
an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected
to external PHY/switch. None of them should be triggered every time an
interface is brought up in ethernet driver.

Remove PHY reset support from ag71xx and definition for them in dtsi.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-08-09 18:44:57 +02:00
Chuanhong Guo
f593020a28 ath79: ag71xx: assert a switch reset if defined in dts.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:35 +02:00
Chuanhong Guo
f43e8f9004 ath79: ag71xx: Explicitly register mdio bus after ag71xx_hw_init() for ar7240
mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?)
Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0
For ar7240 and older chips, manually create platform device after
ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between
ag71xx_hw_init() and ag71xx_phy_connect().

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:35 +02:00
Chuanhong Guo
85189e4c00 ath79: ag71xx: Rework mdio clock settings
Allow specifying desired mdio clock frequency in dts.
Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:34 +02:00
Chuanhong Guo
7ae9e63719 ath79: ag71xx: Make builtin switch driver a separated module
This patch did several things:
1. Probe the builtin switch as a separated mdio device.
2. Register a separated mdio bus for builtin switch.
3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:33 +02:00
Chuanhong Guo
83d2dbc599 ath79: ag71xx: Split mdio driver into an independent platform device.
We need to have mdio1 belonging to gmac1 initialized before gmac0.
Split it into a separated mdio device to get both mdios ready before probing gmac.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:33 +02:00
Chuanhong Guo
24cbe27bb7 ath79: ag71xx: Remove ar7240_set_addr and ag71xx_ar7240_start
The builtin switch has it's initial valid mac address(00:00:01:00:00:00).
Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device.
Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:33 +02:00
Chuanhong Guo
2d081addb5 ath79: ag71xx: Split gmac config into separated file and add support for ar934x/qca955x.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-07-30 10:43:33 +02:00
Lucian Cristian
c8e76cd4ff ath79: fix rx ring buffer stall qca956x
when ported from ar71xx to ath79 the qca9560-eth was omitted

Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
2018-06-18 18:21:20 +02:00
Weijie Gao
52109ce71f ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956x
ar71xx/ar913x series use the old pll registers and settings.

However started from ar7242, a new pll register is introduced and the
pll setting is much simpler.

This can be observed from dev-eth.c from the ar71xx target.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
2018-06-18 18:21:19 +02:00
John Crispin
5a6a32ad9b ath79: fix adjust_link callback for ar9130
Signed-off-by: John Crispin <john@phrozen.org>
2018-05-24 15:43:39 +02:00
Johann Neuhauser
a7e1e919af ath79: preliminary support for TP-Link WDR3600 / WDR4300 (AR9344)
working:
 - leds
 - buttons
 - lan / wan
 - usb (hub port 1 + 2)
 - wifi 5g
 - sysupgrade
 - ...

not working:
 - wifi 2g

Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
2018-05-22 20:53:15 +02:00
Johann Neuhauser
c15dfbeea0 ath79: fix gmac compatible in ar9330.dtsi and ag71xx_setup_gmac_933x
1. compatible property in node gmac was wrong

2. ag71xx_setup_gmac_933x should use np of gmac-config and
   not the pointer to gmac. gmac is only used for the reg address.

Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
2018-05-15 06:38:07 +02:00
John Crispin
53c474abbd ath79: add new OF only target for QCA MIPS silicon
This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>
2018-05-07 08:06:51 +02:00