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ar71xx: fix ethernet packet loss issues on OM5P-AN

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The OM5P-AN boards are suffering from ethernet packet loss when booting with
some active POE setups or when switching to Fast Ethernet when previously
booted with Gigabit ethernet attached.

The cause of the problem is that the AR8035 PHYs requires special register
settings to work reliably on these boards. Enable the RGMII TX, RX delays and
disable SmartEE functionality of the AR8035 PHYs. Also enable the RXD and RDV
delay in the ETH_CFG register to fix the issue.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 45438
This commit is contained in:
John Crispin 2015-04-14 19:00:51 +00:00
parent cc9a392e49
commit efbdc168ff
1 changed files with 21 additions and 1 deletions
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22
target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c
View file

@ -16,6 +16,7 @@
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/i2c-algo-bit.h> #include <linux/i2c-algo-bit.h>
#include <linux/i2c-gpio.h> #include <linux/i2c-gpio.h>
#include <linux/platform_data/phy-at803x.h>
#include <asm/mach-ath79/ar71xx_regs.h> #include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ath79.h>
@ -150,6 +151,20 @@ static struct i2c_board_info om5pan_i2c_devs[] __initdata = {
}, },
}; };
static struct at803x_platform_data om5p_an_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct mdio_board_info om5p_an_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 7,
.platform_data = &om5p_an_at803x_data,
},
};
static void __init om5p_an_setup(void) static void __init om5p_an_setup(void)
{ {
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
@ -171,10 +186,15 @@ static void __init om5p_an_setup(void)
ath79_init_mac(mac, art, 0x02); ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_RXD_DELAY |
AR934X_ETH_CFG_RDV_DELAY);
ath79_register_mdio(0, 0x0); ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0); ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5p_an_mdio0_info,
ARRAY_SIZE(om5p_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);