efbdc168ff
The OM5P-AN boards are suffering from ethernet packet loss when booting with some active POE setups or when switching to Fast Ethernet when previously booted with Gigabit ethernet attached. The cause of the problem is that the AR8035 PHYs requires special register settings to work reliably on these boards. Enable the RGMII TX, RX delays and disable SmartEE functionality of the AR8035 PHYs. Also enable the RXD and RDV delay in the ETH_CFG register to fix the issue. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 45438
219 lines
5.9 KiB
C
219 lines
5.9 KiB
C
/*
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* OpenMesh OM5P support
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*
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* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
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* Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/i2c-gpio.h>
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#include <linux/platform_data/phy-at803x.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define OM5P_GPIO_LED_POWER 13
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#define OM5P_GPIO_LED_GREEN 16
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#define OM5P_GPIO_LED_RED 19
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#define OM5P_GPIO_LED_YELLOW 17
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#define OM5P_GPIO_LED_LAN 14
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#define OM5P_GPIO_LED_WAN 15
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#define OM5P_GPIO_BTN_RESET 4
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#define OM5P_GPIO_I2C_SCL 20
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#define OM5P_GPIO_I2C_SDA 21
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#define OM5P_KEYS_POLL_INTERVAL 20 /* msecs */
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#define OM5P_KEYS_DEBOUNCE_INTERVAL (3 * OM5P_KEYS_POLL_INTERVAL)
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#define OM5P_WMAC_CALDATA_OFFSET 0x1000
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#define OM5P_PCI_CALDATA_OFFSET 0x5000
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static struct gpio_led om5p_leds_gpio[] __initdata = {
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{
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.name = "om5p:blue:power",
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.gpio = OM5P_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "om5p:red:wifi",
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.gpio = OM5P_GPIO_LED_RED,
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.active_low = 1,
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}, {
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.name = "om5p:yellow:wifi",
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.gpio = OM5P_GPIO_LED_YELLOW,
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.active_low = 1,
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}, {
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.name = "om5p:green:wifi",
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.gpio = OM5P_GPIO_LED_GREEN,
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.active_low = 1,
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}, {
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.name = "om5p:blue:lan",
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.gpio = OM5P_GPIO_LED_LAN,
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.active_low = 1,
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}, {
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.name = "om5p:blue:wan",
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.gpio = OM5P_GPIO_LED_WAN,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button om5p_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = OM5P_KEYS_DEBOUNCE_INTERVAL,
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.gpio = OM5P_GPIO_BTN_RESET,
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.active_low = 1,
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}
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};
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static struct flash_platform_data om5p_flash_data = {
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.type = "mx25l12805d",
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};
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static void __init om5p_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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/* make lan / wan leds software controllable */
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ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
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ath79_register_m25p80(&om5p_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
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om5p_leds_gpio);
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ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om5p_gpio_keys),
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om5p_gpio_keys);
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ath79_init_mac(mac, art, 2);
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ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
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/* GMAC0 is connected to the PHY0 of the internal switch */
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ath79_switch_data.phy4_mii_en = 1;
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ath79_switch_data.phy_poll_mask = BIT(0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(0);
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/* GMAC1 is connected to the internal switch */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_OM5P, "OM5P", "OpenMesh OM5P", om5p_setup);
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static struct i2c_gpio_platform_data om5pan_i2c_device_platdata = {
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.sda_pin = OM5P_GPIO_I2C_SDA,
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.scl_pin = OM5P_GPIO_I2C_SCL,
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.udelay = 10,
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.sda_is_open_drain = 1,
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.scl_is_open_drain = 1,
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};
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static struct platform_device om5pan_i2c_device = {
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.name = "i2c-gpio",
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.id = 0,
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.dev = {
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.platform_data = &om5pan_i2c_device_platdata,
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},
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};
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static struct i2c_board_info om5pan_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("tmp423", 0x4c),
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},
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};
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static struct at803x_platform_data om5p_an_at803x_data = {
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.disable_smarteee = 1,
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.enable_rgmii_rx_delay = 1,
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.enable_rgmii_tx_delay = 1,
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};
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static struct mdio_board_info om5p_an_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 7,
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.platform_data = &om5p_an_at803x_data,
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},
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};
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static void __init om5p_an_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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/* temperature sensor */
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platform_device_register(&om5pan_i2c_device);
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i2c_register_board_info(0, om5pan_i2c_devs,
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ARRAY_SIZE(om5pan_i2c_devs));
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/* make lan / wan leds software controllable */
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ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
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ath79_register_m25p80(&om5p_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
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om5p_leds_gpio);
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ath79_init_mac(mac, art, 0x02);
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ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
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AR934X_ETH_CFG_RXD_DELAY |
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AR934X_ETH_CFG_RDV_DELAY);
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ath79_register_mdio(0, 0x0);
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ath79_register_mdio(1, 0x0);
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mdiobus_register_board_info(om5p_an_mdio0_info,
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ARRAY_SIZE(om5p_an_mdio0_info));
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ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
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ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
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/* GMAC0 is connected to the PHY7 */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_data.phy_mask = BIT(7);
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ath79_eth0_pll_data.pll_1000 = 0x1a000000;
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ath79_eth0_pll_data.pll_100 = 0x00000101;
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ath79_eth0_pll_data.pll_10 = 0x00001313;
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ath79_register_eth(0);
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/* GMAC1 is connected to the internal switch */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(1);
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ath79_init_mac(mac, art, 0x10);
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ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac);
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}
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MIPS_MACHINE(ATH79_MACH_OM5P_AN, "OM5P-AN", "OpenMesh OM5P AN", om5p_an_setup);
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