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ipq806x: add ipq4019 support

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Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
Christian Lamparter 2017-03-14 17:02:20 +01:00 committed by John Crispin
parent 5c617aec05
commit c2d50bdeb3
29 changed files with 21249 additions and 327 deletions
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8
target/linux/ipq806x/config-4.9
View file

@ -2,6 +2,7 @@ CONFIG_ALIGNMENT_TRAP=y
# CONFIG_AMBA_PL08X is not set
CONFIG_APQ_GCC_8084=y
CONFIG_APQ_MMCC_8084=y
CONFIG_AR40XX_PHY=y
CONFIG_AR8216_PHY=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
@ -10,6 +11,7 @@ CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MSM8960=y
@ -66,6 +68,7 @@ CONFIG_BLK_MQ_PCI=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_BOUNCE=y
CONFIG_BUS_TOPOLOGY_ADHOC=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_OF=y
@ -143,6 +146,7 @@ CONFIG_DYNAMIC_DEBUG=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_ESSEDMA=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
@ -253,6 +257,7 @@ CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ40XX=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
# CONFIG_MFD_MAX77620 is not set
@ -272,6 +277,7 @@ CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MSM_BUS_SCALING=y
CONFIG_MSM_GCC_8660=y
# CONFIG_MSM_GCC_8916 is not set
CONFIG_MSM_GCC_8960=y
@ -291,6 +297,7 @@ CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOM_SMEM_PARTS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware"
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
@ -389,6 +396,7 @@ CONFIG_QCOM_SCM_32=y
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMP2P is not set
# CONFIG_QCOM_SMSM is not set
CONFIG_QCOM_TCSR=y
CONFIG_QCOM_TSENS=y
# CONFIG_QCOM_WCNSS_PIL is not set
CONFIG_QCOM_WDT=y

1142
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi Normal file
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File diff suppressed because it is too large Load diff

293
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts Normal file
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@ -0,0 +1,293 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019-ap.dk01.1.dtsi"
#include "qcom-ipq4019-bus.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Box 4040";
compatible = "avm,fritzbox-4040", "qcom,ipq4019";
reserved-memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
rsvd1@87000000 {
reg = <0x87000000 0x500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
reg = <0x87b00000 0x500000>;
no-map;
};
};
/*
This also works. Maybe it could be smaller still.
reserved-memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
rsvd1@87E00000 {
reg = <0x87e00000 0x200000>;
no-map;
};
};
*/
soc {
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "ok";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
mdio@90000 {
status = "okay";
};
qca8075: ess-switch@c000000 {
status = "okay";
#gpio-cells = <2>;
gpio-controller;
enable-usb-power {
gpio-hog;
line-name = "enable USB3 power";
gpios = <0x7 GPIO_ACTIVE_HIGH>;
output-high;
};
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
wifi@a000000 {
status = "okay";
};
wifi@a800000 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 0x3a GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
aliases {
led-boot = &power;
led-failsafe = &flash;
led-running = &power;
led-upgrade = &flash;
};
gpio-leds {
compatible = "gpio-leds";
wlan {
label = "fritz4040:green:wlan";
gpios = <&qca8075 0x1 GPIO_ACTIVE_HIGH>;
};
panic: info_red {
label = "fritz4040:red:info";
gpios = <&qca8075 0x3 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
wan {
label = "fritz4040:green:wan";
gpios = <&qca8075 0x5 GPIO_ACTIVE_HIGH>;
};
power: power {
label = "fritz4040:green:power";
gpios = <&qca8075 0xb GPIO_ACTIVE_HIGH>;
};
lan {
label = "fritz4040:green:lan";
gpios = <&qca8075 0xd GPIO_ACTIVE_HIGH>;
};
flash: info_amber {
label = "fritz4040:amber:info";
gpios = <&qca8075 0xf GPIO_ACTIVE_HIGH>;
};
};
};
&spi_0 { /* BLSP1 QUP1 */
status = "ok";
mx25l25635e@0 {
status = "disabled";
};
mx25l25635f@0 {
compatible = "mx25l25635f", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
spi-max-frequency = <24000000>;
status = "ok";
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBLENV"; /* uboot env - empty */
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "urlader"; /* APPSBL */
reg = <0x000f0000 0x0002dc000>;
read-only;
};
partition7@11dc00 {
/* make a backup of this partition! */
label = "urlader_config";
reg = <0x0011dc00 0x00002400>;
read-only;
};
partition8@120000 {
label = "tffs1";
reg = <0x00120000 0x00080000>;
read-only;
};
partition9@1a0000 {
label = "tffs2";
reg = <0x001a0000 0x00080000>;
read-only;
};
partition10@220000 {
label = "uboot";
reg = <0x00220000 0x00080000>;
read-only;
};
partition11@2A0000 {
label = "image"; /* firmware */
reg = <0x002A0000 0x01C60000>;
};
partition12@1f00000 {
label = "jffs2";
reg = <0x01F00000 0x00100000>;
};
};
};
};
&cpu0_opp_table {
/delete-node/ opp@666000000;
opp@710000000 {
opp-hz = /bits/ 64 <710000000>;
clock-latency-ns = <256000>;
};
};

208
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-nbg6617.dts Normal file
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@ -0,0 +1,208 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019-ap.dk01.1.dtsi"
#include "qcom-ipq4019-bus.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ZyXEL NBG6617";
compatible = "zyxel,nbg6617", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
reserved-memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
rsvd1@87000000 {
reg = <0x87000000 0x0500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
reg = <0x87b00000 0x500000>;
no-map;
};
};
soc {
pinctrl@0x01000000 {
led_pinmux {
mux {
pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
drive-strength = <0x8>;
bias-pull-up;
output-high;
};
};
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "ok";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
mdio@90000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
wifi@a000000 {
status = "okay";
};
wifi@a800000 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 0x2 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 0x3f GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 0x4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
gpio-leds {
compatible = "gpio-leds";
power: power {
label = "nbg6617:green:power";
gpios = <&tlmm 0x3 GPIO_ACTIVE_HIGH>;
};
wps {
label = "nbg6617:green:wps";
gpios = <&tlmm 0x1 GPIO_ACTIVE_HIGH>;
};
wlan2G {
label = "nbg6617:green:wlan2G";
gpios = <&tlmm 0x3a GPIO_ACTIVE_HIGH>;
};
wlan5G {
label = "nbg6617:green:wlan5G";
gpios = <&tlmm 0x5 GPIO_ACTIVE_HIGH>;
};
};
};
&spi_0 { /* BLSP1 QUP1 */
status = "ok";
mx25l25635e@0 {
status = "disabled";
};
n25q128a11@0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "all";
reg = <0x00000000 0x08000000>;
read-only; /* for now */
};
};
};
};

271
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-rt-ac58u.dts Normal file
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@ -0,0 +1,271 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019-ap.dk01.1.dtsi"
#include "qcom-ipq4019-bus.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ASUS RT-AC58U";
compatible = "asus,rt-ac58u", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
reserved-memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
rsvd1@87E00000 {
reg = <0x87e00000 0x200000>;
no-map;
};
};
soc {
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "ok";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
mdio@90000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
wifi@a000000 {
status = "okay";
};
wifi@a800000 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
gpio-leds {
compatible = "gpio-leds";
power: status {
label = "rt-ac58u:blue:status";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wan {
label = "rt-ac58u:blue:wan";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan2G {
label = "rt-ac58u:blue:wlan2G";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
wan5G {
label = "rt-ac58u:blue:wlan5G";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
usb {
label = "rt-ac58u:blue:usb";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
lan {
label = "rt-ac58u:blue:lan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&spi_0_pins {
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
};
pinconf_cs {
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
&spi_0 { /* BLSP1 QUP1 */
status = "ok";
cs-gpios = <&tlmm 54 0>,
<&tlmm 59 0>;
mx25l25635e@0 {
status = "disabled";
};
m25p80@0 {
#address-cells = <1>;
#size-cells = <0>;
/*
* U-boot looks for "n25q128a11" node,
* if we don't have it, it will spit out the following warning:
* "ipq: fdt fixup unable to find compatible node".
*/
compatible = "mx25l1606e", "n25q128a11";
reg = <0>;
linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition5@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition5@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
/* 0x00180000 - 0x00200000 unused */
};
};
mt29f@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "spinand,mt29f", "w25n01gv";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
};
};
};
};

2
target/linux/ipq806x/patches-4.9/0022-dts-ipq4019-support-ARMv7-PMU.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -118,6 +118,12 @@
@@ -108,6 +108,12 @@
IRQ_TYPE_LEVEL_HIGH)>;
};

87
target/linux/ipq806x/patches-4.9/0024-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
View file

@ -1,87 +0,0 @@
From 0fba6eceb6e16fa8fd5834d65fcb771fa263a44b Mon Sep 17 00:00:00 2001
From: Matthew McClintock <mmcclint@codeaurora.org>
Date: Thu, 17 Mar 2016 16:22:28 -0500
Subject: [PATCH 24/69] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
This adds the SoC nodes to the ipq4019 device tree
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 67 +++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -313,5 +313,72 @@
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qca,uni-ssphy";
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qca,baldur-usb3-hsphy";
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>;
+ clock-names = "core";
+ ranges;
+ status = "disabled";
+
+ dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <0 132 0>;
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qca,baldur-usb2-hsphy";
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>;
+ clock-names = "core";
+ ranges;
+ status = "disabled";
+
+ dwc3@6000000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <0 136 0>;
+ usb-phy = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ dr_mode = "host";
+ };
+ };
};
};

45
target/linux/ipq806x/patches-4.9/0025-qcom-ipq4019-enable-USB-bus-for-DK01.1-board.patch
View file

@ -1,45 +0,0 @@
From ae5e11c926f710595d0080e51bd10e704776669d Mon Sep 17 00:00:00 2001
From: Matthew McClintock <mmcclint@codeaurora.org>
Date: Mon, 21 Mar 2016 16:12:05 -0500
Subject: [PATCH 25/69] qcom: ipq4019: enable USB bus for DK01.1 board
This enables the USB block
Change-Id: I384dd1874bba341713f384cf6199abd446e3f3c0
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -108,5 +108,29 @@
watchdog@b017000 {
status = "ok";
};
+
+ usb3_ss_phy: ssphy@0 {
+ status = "ok";
+ };
+
+ dummy_ss_phy: ssphy@1 {
+ status = "ok";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "ok";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "ok";
+ };
+
+ usb3: usb3@8a00000 {
+ status = "ok";
+ };
+
+ usb2: usb2@6000000 {
+ status = "ok";
+ };
};
};

38
target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
View file

@ -32,40 +32,6 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,11 +109,7 @@
status = "ok";
};
- usb3_ss_phy: ssphy@0 {
- status = "ok";
- };
-
- dummy_ss_phy: ssphy@1 {
+ usb3_ss_phy: ssphy@9a000 {
status = "ok";
};
@@ -121,15 +117,15 @@
status = "ok";
};
- usb2_hs_phy: hsphy@a8000 {
+ usb3@0 {
status = "ok";
};
- usb3: usb3@8a00000 {
+ usb2_hs_phy: hsphy@a8000 {
status = "ok";
};
- usb2: usb2@6000000 {
+ usb2@0{
status = "ok";
};
};
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,21 @@
@ -231,7 +197,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+ status = "ok";
+ };
+
+ usb3: usb3@0 {
+ usb3: usb3@8af8800 {
+ status = "ok";
+ };
+
@ -239,7 +205,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+ status = "ok";
+ };
+
+ usb2: usb2@6000000 {
+ usb2: usb2@60f8800 {
+ status = "ok";
+ };
+

6
target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
View file

@ -10,9 +10,13 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -619,6 +619,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
@@ -618,7 +618,18 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-fritz4040.dtb \
+ qcom-ipq4019-nbg6617.dtb \
+ qcom-ipq4019-rt-ac58u.dtb \
qcom-ipq8064-ap148.dtb \
+ qcom-ipq8064-c2600.dtb \
+ qcom-ipq8064-d7800.dtb \

56
target/linux/ipq806x/patches-4.9/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch Normal file
View file

@ -0,0 +1,56 @@
From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Mon, 14 Nov 2016 23:49:22 +0100
Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
This patch adds the W25N01GV NAND to the table of
known devices. Without this patch the device gets detected:
nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
nand: Unknown NAND 256MiB 1,8V 8-bit
nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
Whereas the u-boot identifies it as:
spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
Due to the page size discrepancy, it's impossible to attach
ubi volumes on the device.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/mtd/nand/nand_ids.c | 4 ++++
include/linux/mtd/nand.h | 1 +
2 files changed, 5 insertions(+)
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -52,6 +52,10 @@ struct nand_flash_dev nand_flash_ids[] =
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
NAND_ECC_INFO(40, SZ_1K), 4 },
+ {"W25N01GV 1G 3.3V 8-bit",
+ { .id = {0xef, 0xaa} },
+ SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
+ 2, 64, NAND_ECC_INFO(1, SZ_512) },
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
@@ -182,6 +186,7 @@ struct nand_manufacturers nand_manuf_ids
{NAND_MFR_SANDISK, "SanDisk"},
{NAND_MFR_INTEL, "Intel"},
{NAND_MFR_ATO, "ATO"},
+ {NAND_MFR_WINBOND, "Winbond"},
{0x0, "Unknown"}
};
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -924,6 +924,7 @@ static inline void nand_set_controller_d
#define NAND_MFR_MICRON 0x2c
#define NAND_MFR_AMD 0x01
#define NAND_MFR_MACRONIX 0xc2
+#define NAND_MFR_WINBOND 0xef
#define NAND_MFR_EON 0x92
#define NAND_MFR_SANDISK 0x45
#define NAND_MFR_INTEL 0x89

22
target/linux/ipq806x/patches-4.9/105-mtd-nor-add-mx25l25635f.patch Normal file
View file

@ -0,0 +1,22 @@
Subject: mtd: spi-nor: add mx25l25635f with SECT_4K
This patch fixes an issue with the creation of the
ubi volume on the AVM FRITZ!Box 4040. The mx25l25635f
and mx25l25635e support SECT_4K which will set the
erase size to 4K. This is used by ubi to calculate
VID header offsets. Without this, uboot and linux
disagrees about the layout and refuse to attach
the ubi volume created by the other.
---
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1018,7 +1018,7 @@ static const struct flash_info spi_nor_i
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
- { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
+ { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512, SECT_4K) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },

51
target/linux/ipq806x/patches-4.9/130-pinctrl-ipq4019-add-pinctrl.patch Normal file
View file

@ -0,0 +1,51 @@
From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Thu, 16 Mar 2017 21:00:18 +0100
Subject: [PATCH] pinctrl: ipq4019: Add missing pingroups
This patch adds the missing PINGROUP for GPIO70-99.
This fixes a crash that happens in pinctrl-msm, if any
of the GPIO70-99 are accessed.
Fixes: 5303f7827fcd41d ("pinctrl: qcom: ipq4019: set ngpios to correct value")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -405,6 +405,36 @@ static const struct msm_pingroup ipq4019
PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
};
static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {

47
target/linux/ipq806x/patches-4.9/0021-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch → target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
View file

@ -1,19 +1,23 @@
From 644ad7209637b02a0ca6d72f0715a9f52532fc70 Mon Sep 17 00:00:00 2001
From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
From: Matthew McClintock <mmcclint@codeaurora.org>
Date: Fri, 8 Apr 2016 15:26:10 -0500
Subject: [PATCH 21/69] qcom: ipq4019: use v2 of the kpss bringup mechanism
Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
v1 was the incorrect choice here and sometimes the board would not come
up properly
v1 was the incorrect choice here and sometimes the board
would not come up properly.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
Changes:
- moved L2-Cache to be a subnode of cpu0
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -34,7 +34,8 @@
@@ -34,19 +34,27 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -23,7 +27,17 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
reg = <0x0>;
@@ -46,7 +47,8 @@
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
operating-points-v2 = <&cpu0_opp_table>;
+
+ L2: l2-cache {
+ compatible = "qcom,arch-cache";
+ cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+ };
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -33,7 +47,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
@@ -58,7 +60,8 @@
@@ -58,7 +66,8 @@
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -43,7 +57,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
@@ -70,7 +73,8 @@
@@ -70,7 +79,8 @@
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@ -53,20 +67,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
reg = <0x3>;
@@ -100,6 +104,12 @@
opp-hz = /bits/ 64 <666000000>;
clock-latency-ns = <256000>;
};
+
+ L2: l2-cache {
+ compatible = "qcom,arch-cache";
+ cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+ };
};
pmu {
@@ -212,22 +222,22 @@
@@ -218,22 +228,22 @@
};
acc0: clock-controller@b088000 {
@ -93,7 +94,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
@@ -255,6 +265,12 @@
@@ -261,6 +271,12 @@
regulator;
};

130
target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch Normal file
View file

@ -0,0 +1,130 @@
From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
From: Matthew McClintock <mmcclint@codeaurora.org>
Date: Thu, 17 Mar 2016 16:22:28 -0500
Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
This adds the SoC nodes to the ipq4019 device tree and
enable it for the DK01.1 board.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
Changes:
- replaced space with tab
- added sleep and mock_utmi clocks
- added registers for usb2 and usb3 parent node
- changed compatible to qca,ipa4019-dwc3
- updated usb2 and usb3 names
(included the reg - in case they become necessary later)
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
2 files changed, 91 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -108,5 +108,25 @@
watchdog@b017000 {
status = "ok";
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "ok";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "ok";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "ok";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "ok";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "ok";
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -313,5 +313,76 @@
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qca,uni-ssphy";
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qca,baldur-usb3-hsphy";
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3@8af8800 {
+ compatible = "qca,ipq4019-dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
+ <&gcc GCC_USB3_SLEEP_CLK>,
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <0 132 0>;
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qca,baldur-usb2-hsphy";
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2@60f8800 {
+ compatible = "qca,ipq4019-dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
+ <&gcc GCC_USB2_SLEEP_CLK>,
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@6000000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <0 136 0>;
+ usb-phy = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};

35
target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch Normal file
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@ -0,0 +1,35 @@
From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 00:58:18 +0100
Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
Add support for the Qualcomm Atheros IPQ4019 SoC.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/Makefile | 1 +
arch/arm/mach-qcom/Kconfig | 5 +++++
2 files changed, 6 insertions(+)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
endif
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -28,4 +28,9 @@ config ARCH_MDM9615
bool "Enable support for MDM9615"
select CLKSRC_QCOM
+config ARCH_IPQ40XX
+ bool "Enable support for IPQ40XX"
+ select CLKSRC_QCOM
+ select HAVE_ARM_ARCH_TIMER
+
endif

105
target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch Normal file
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@ -0,0 +1,105 @@
From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 01:22:46 +0100
Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
are already supported by ath10k.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -384,5 +384,89 @@
dr_mode = "host";
};
};
+
+ wifi0: wifi@a000000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa000000 0x200000>;
+ resets = <&gcc WIFI0_CPU_INIT_RESET
+ &gcc WIFI0_RADIO_SRIF_RESET
+ &gcc WIFI0_RADIO_WARM_RESET
+ &gcc WIFI0_RADIO_COLD_RESET
+ &gcc WIFI0_CORE_WARM_RESET
+ &gcc WIFI0_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS2G_CLK
+ &gcc GCC_WCSS2G_REF_CLK
+ &gcc GCC_WCSS2G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING
+ 0 33 IRQ_TYPE_EDGE_RISING
+ 0 34 IRQ_TYPE_EDGE_RISING
+ 0 35 IRQ_TYPE_EDGE_RISING
+ 0 36 IRQ_TYPE_EDGE_RISING
+ 0 37 IRQ_TYPE_EDGE_RISING
+ 0 38 IRQ_TYPE_EDGE_RISING
+ 0 39 IRQ_TYPE_EDGE_RISING
+ 0 40 IRQ_TYPE_EDGE_RISING
+ 0 41 IRQ_TYPE_EDGE_RISING
+ 0 42 IRQ_TYPE_EDGE_RISING
+ 0 43 IRQ_TYPE_EDGE_RISING
+ 0 44 IRQ_TYPE_EDGE_RISING
+ 0 45 IRQ_TYPE_EDGE_RISING
+ 0 46 IRQ_TYPE_EDGE_RISING
+ 0 47 IRQ_TYPE_EDGE_RISING
+ 0 168 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+ "msi12", "msi13", "msi14", "msi15",
+ "legacy";
+ status = "disabled";
+ };
+
+ wifi1: wifi@a800000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa800000 0x200000>;
+ resets = <&gcc WIFI1_CPU_INIT_RESET
+ &gcc WIFI1_RADIO_SRIF_RESET
+ &gcc WIFI1_RADIO_WARM_RESET
+ &gcc WIFI1_RADIO_COLD_RESET
+ &gcc WIFI1_CORE_WARM_RESET
+ &gcc WIFI1_CORE_COLD_RESET>;
+ reset-names = "wifi_cpu_init", "wifi_radio_srif",
+ "wifi_radio_warm", "wifi_radio_cold",
+ "wifi_core_warm", "wifi_core_cold";
+ clocks = <&gcc GCC_WCSS5G_CLK
+ &gcc GCC_WCSS5G_REF_CLK
+ &gcc GCC_WCSS5G_RTC_CLK>;
+ clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
+ "wifi_wcss_rtc";
+ interrupts = <0 48 IRQ_TYPE_EDGE_RISING
+ 0 49 IRQ_TYPE_EDGE_RISING
+ 0 50 IRQ_TYPE_EDGE_RISING
+ 0 51 IRQ_TYPE_EDGE_RISING
+ 0 52 IRQ_TYPE_EDGE_RISING
+ 0 53 IRQ_TYPE_EDGE_RISING
+ 0 54 IRQ_TYPE_EDGE_RISING
+ 0 55 IRQ_TYPE_EDGE_RISING
+ 0 56 IRQ_TYPE_EDGE_RISING
+ 0 57 IRQ_TYPE_EDGE_RISING
+ 0 58 IRQ_TYPE_EDGE_RISING
+ 0 59 IRQ_TYPE_EDGE_RISING
+ 0 60 IRQ_TYPE_EDGE_RISING
+ 0 61 IRQ_TYPE_EDGE_RISING
+ 0 62 IRQ_TYPE_EDGE_RISING
+ 0 63 IRQ_TYPE_EDGE_RISING
+ 0 169 IRQ_TYPE_NONE>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+ "msi12", "msi13", "msi14", "msi15",
+ "legacy";
+ status = "disabled";
+ };
};
};

29
target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch Normal file
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@ -0,0 +1,29 @@
From 26fa6fdc627b523277c7a79907233596b2f8a3ef Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 03:29:04 +0100
Subject: [PATCH] dts: ipq4019: add pseudo random number generator
This architecture has a pseudo random number generator
supported by the existing "qcom,prng" binding.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -277,6 +277,13 @@
regulator;
};
+ rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x22000 0x140>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;

11026
target/linux/ipq806x/patches-4.9/310-msm-adhoc-bus-support.patch Normal file
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29
target/linux/ipq806x/patches-4.9/400-mtd-ubi-add-quirk-to-autoload-ubi-on-rt-ac58u.patch Normal file
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@ -0,0 +1,29 @@
From b8f3a7ccbeca5bdbd1b6210b94b38d3fef2dd0bd Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Thu, 19 Jan 2017 01:57:22 +0100
Subject: [PATCH 16/38] mtd: ubi: add auto_attach HACK for the ASUS RT-AC58U
This patch adds a hack that allows UBI's autoattach feature
to work with the custom ASUS UBI_DEV partition name.
This is necessary because the vendor's u-boot doesn't leave
the bootargs / cmdline alone, so the it can't be overwritten
easily otherwise.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
drivers/mtd/ubi/build.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -1225,6 +1225,9 @@ static void __init ubi_auto_attach(void)
mtd = open_mtd_device("ubi");
if (IS_ERR(mtd))
mtd = open_mtd_device("data");
+ /* Hack for the Asus RT-AC58U */
+ if (IS_ERR(mtd))
+ mtd = open_mtd_device("UBI_DEV");
if (!IS_ERR(mtd)) {
size_t len;

53
target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch Normal file
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@ -0,0 +1,53 @@
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
From: Rakesh Nair <ranair@codeaurora.org>
Date: Wed, 20 Jul 2016 15:02:01 +0530
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
netdev_ops
Add callback support to get default vlan tag and register
receive flow steering filter.
Used by IPQ4019 ess-edma driver.
BUG=chrome-os-partner:33096
TEST=none
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/362203
Commit-Ready: Grant Grundler <grundler@chromium.org>
Tested-by: Grant Grundler <grundler@chromium.org>
Reviewed-by: Grant Grundler <grundler@chromium.org>
---
include/linux/netdevice.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -725,6 +725,16 @@ struct xps_map {
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
- sizeof(struct xps_map)) / sizeof(u16))
+#ifdef CONFIG_RFS_ACCEL
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
+ __be32 src,
+ __be32 dst,
+ __be16 sport,
+ __be16 dport,
+ u8 proto,
+ u16 rxq_index,
+ u32 action);
+#endif
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.
*/
@@ -1250,6 +1260,9 @@ struct net_device_ops {
const struct sk_buff *skb,
u16 rxq_index,
u32 flow_id);
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
+ set_rfs_filter_callback_t set_filter);
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
#endif
int (*ndo_add_slave)(struct net_device *dev,
struct net_device *slave_dev);

2690
target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch Normal file
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52
target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch Normal file
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@ -0,0 +1,52 @@
From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 01:10:33 +0100
Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
This patch adds the mdio device-tree node.
This is where the switch is connected to, so it's needed
for the ethernet interfaces.
Note: The driver isn't anywhere close to be upstream,
so the info might change.
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -321,6 +321,34 @@
reg = <0x4ab000 0x4>;
};
+ mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x90000 0x64>;
+ status = "disabled";
+
+ ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ ethernet-phy@4 {
+ reg = <4>;
+ };
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qca,uni-ssphy";
reg = <0x9a000 0x800>;

46
target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch Normal file
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@ -0,0 +1,46 @@
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 02:20:54 +0100
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
nodes which are needed for the ar40xx.c driver to initialize the
switch.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -349,6 +349,29 @@
};
};
+ ess-switch@c000000 {
+ compatible = "qcom,ess-switch";
+ reg = <0xc000000 0x80000>;
+ switch_access_mode = "local bus";
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
+ switch_initvlas = <0x7c 0x54>;
+ status = "disabled";
+ };
+
+ ess-psgmii@98000 {
+ compatible = "qcom,ess-psgmii";
+ reg = <0x98000 0x800>;
+ psgmii_access_mode = "local bus";
+ status = "disabled";
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qca,uni-ssphy";
reg = <0x9a000 0x800>;

4602
target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch Normal file
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File diff suppressed because it is too large Load diff

92
target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch Normal file
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@ -0,0 +1,92 @@
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 01:01:10 +0100
Subject: [PATCH] dts: ipq4019: add ethernet essedma node
This patch adds the device-tree node for the ethernet
interfaces.
Note: The driver isn't anywhere close to be upstream,
so the info might change.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -26,6 +26,8 @@
aliases {
spi0 = &spi_0;
i2c0 = &i2c_0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
cpus {
@@ -372,6 +374,64 @@
status = "disabled";
};
+ edma@c080000 {
+ compatible = "qcom,ess-edma";
+ reg = <0xc080000 0x8000>;
+ qcom,page-mode = <0>;
+ qcom,rx_head_buf_size = <1540>;
+ qcom,mdio_supported;
+ qcom,poll_required = <1>;
+ qcom,num_gmac = <2>;
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
+ 0 66 IRQ_TYPE_EDGE_RISING
+ 0 67 IRQ_TYPE_EDGE_RISING
+ 0 68 IRQ_TYPE_EDGE_RISING
+ 0 69 IRQ_TYPE_EDGE_RISING
+ 0 70 IRQ_TYPE_EDGE_RISING
+ 0 71 IRQ_TYPE_EDGE_RISING
+ 0 72 IRQ_TYPE_EDGE_RISING
+ 0 73 IRQ_TYPE_EDGE_RISING
+ 0 74 IRQ_TYPE_EDGE_RISING
+ 0 75 IRQ_TYPE_EDGE_RISING
+ 0 76 IRQ_TYPE_EDGE_RISING
+ 0 77 IRQ_TYPE_EDGE_RISING
+ 0 78 IRQ_TYPE_EDGE_RISING
+ 0 79 IRQ_TYPE_EDGE_RISING
+ 0 80 IRQ_TYPE_EDGE_RISING
+ 0 240 IRQ_TYPE_EDGE_RISING
+ 0 241 IRQ_TYPE_EDGE_RISING
+ 0 242 IRQ_TYPE_EDGE_RISING
+ 0 243 IRQ_TYPE_EDGE_RISING
+ 0 244 IRQ_TYPE_EDGE_RISING
+ 0 245 IRQ_TYPE_EDGE_RISING
+ 0 246 IRQ_TYPE_EDGE_RISING
+ 0 247 IRQ_TYPE_EDGE_RISING
+ 0 248 IRQ_TYPE_EDGE_RISING
+ 0 249 IRQ_TYPE_EDGE_RISING
+ 0 250 IRQ_TYPE_EDGE_RISING
+ 0 251 IRQ_TYPE_EDGE_RISING
+ 0 252 IRQ_TYPE_EDGE_RISING
+ 0 253 IRQ_TYPE_EDGE_RISING
+ 0 254 IRQ_TYPE_EDGE_RISING
+ 0 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ gmac0: gmac0 {
+ local-mac-address = [00 00 00 00 00 00];
+ vlan_tag = <1 0x1f>;
+ };
+
+ gmac1: gmac1 {
+ local-mac-address = [00 00 00 00 00 00];
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+ };
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qca,uni-ssphy";
reg = <0x9a000 0x800>;

87
target/linux/ipq806x/patches-4.9/0023-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch → target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
View file

@ -1,18 +1,24 @@
From 04d3f9be0ce80fac99d4ca1f46faf3605258ca1f Mon Sep 17 00:00:00 2001
From e73682ec4455c34f3f3edc7f40d90ed297521012 Mon Sep 17 00:00:00 2001
From: Senthilkumar N L <snlakshm@codeaurora.org>
Date: Tue, 6 Jan 2015 12:52:23 +0530
Subject: [PATCH 23/69] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
Subject: [PATCH] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
These drivers handles control and configuration of the HS
and SS USB PHY transceivers.
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
Changed:
- replaced spaces with tabs
- remove emulation and host variables
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile | 2 +
drivers/usb/phy/phy-qca-baldur.c | 262 +++++++++++++++++++++++++++++++++++++++
drivers/usb/phy/phy-qca-uniphy.c | 171 +++++++++++++++++++++++++
4 files changed, 446 insertions(+)
drivers/usb/phy/phy-qca-baldur.c | 233 +++++++++++++++++++++++++++++++++++++++
drivers/usb/phy/phy-qca-uniphy.c | 141 +++++++++++++++++++++++
4 files changed, 387 insertions(+)
create mode 100644 drivers/usb/phy/phy-qca-baldur.c
create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
@ -49,7 +55,7 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
--- /dev/null
+++ b/drivers/usb/phy/phy-qca-baldur.c
@@ -0,0 +1,262 @@
@@ -0,0 +1,233 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
@ -88,14 +94,6 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+#define PHY_MISC_ADDR 0x024
+#define PHY_IPG_ADDR 0x030
+
+#define PHY_CTRL0_EMU_ADDR 0x180
+#define PHY_CTRL1_EMU_ADDR 0x184
+#define PHY_CTRL2_EMU_ADDR 0x188
+#define PHY_CTRL3_EMU_ADDR 0x18C
+#define PHY_CTRL4_EMU_ADDR 0x190
+#define PHY_MISC_EMU_ADDR 0x1A4
+#define PHY_IPG_EMU_ADDR 0x1B0
+
+#define PHY_CTRL0_VAL 0xA4600015
+#define PHY_CTRL1_VAL 0x09500000
+#define PHY_CTRL2_VAL 0x00058180
@ -104,14 +102,6 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+#define PHY_MISC_VAL 0x3803FB0C
+#define PHY_IPG_VAL 0x47323232
+
+#define PHY_CTRL0_EMU_VAL 0xb4000015
+#define PHY_CTRL1_EMU_VAL 0x09500000
+#define PHY_CTRL2_EMU_VAL 0x00058180
+#define PHY_CTRL3_EMU_VAL 0x6DB6DCD6
+#define PHY_CTRL4_EMU_VAL 0x836DB6DB
+#define PHY_MISC_EMU_VAL 0x3803FB0C
+#define PHY_IPG_EMU_VAL 0x47323232
+
+#define USB30_HS_PHY_HOST_MODE (0x01 << 21)
+#define USB20_HS_PHY_HOST_MODE (0x01 << 5)
+
@ -131,8 +121,6 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+ struct reset_control *por_rst;
+ struct reset_control *srif_rst;
+
+ unsigned int host;
+ unsigned int emulation;
+ const struct qca_baldur_hs_data *data;
+};
+
@ -169,7 +157,6 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+ reset_control_deassert(phy->srif_rst);
+ msleep(10);
+
+ if (!phy->emulation) {
+ /* perform PHY register writes */
+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
@ -178,16 +165,6 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
+ } else {
+ /* perform PHY register writes */
+ writel(PHY_CTRL0_EMU_VAL, phy->base + PHY_CTRL0_EMU_ADDR);
+ writel(PHY_CTRL1_EMU_VAL, phy->base + PHY_CTRL1_EMU_ADDR);
+ writel(PHY_CTRL2_EMU_VAL, phy->base + PHY_CTRL2_EMU_ADDR);
+ writel(PHY_CTRL3_EMU_VAL, phy->base + PHY_CTRL3_EMU_ADDR);
+ writel(PHY_CTRL4_EMU_VAL, phy->base + PHY_CTRL4_EMU_ADDR);
+ writel(PHY_MISC_EMU_VAL, phy->base + PHY_MISC_EMU_ADDR);
+ writel(PHY_IPG_EMU_VAL, phy->base + PHY_IPG_EMU_ADDR);
+ }
+
+ msleep(10);
+
@ -314,7 +291,7 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
--- /dev/null
+++ b/drivers/usb/phy/phy-qca-uniphy.c
@@ -0,0 +1,171 @@
@@ -0,0 +1,135 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
@ -349,38 +326,10 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+ void __iomem *base;
+
+ struct reset_control *por_rst;
+
+ unsigned int host;
+};
+
+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
+
+/**
+ * Write register
+ *
+ * @base - PHY base virtual address.
+ * @offset - register offset.
+ */
+static u32 qca_uni_ss_read(void __iomem *base, u32 offset)
+{
+ u32 value;
+ value = readl_relaxed(base + offset);
+ return value;
+}
+
+/**
+ * Write register
+ *
+ * @base - PHY base virtual address.
+ * @offset - register offset.
+ * @val - value to write.
+ */
+static void qca_uni_ss_write(void __iomem *base, u32 offset, u32 val)
+{
+ writel(val, base + offset);
+ udelay(100);
+}
+
+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
+{
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
@ -396,9 +345,7 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+ /* assert SS PHY POR reset */
+ reset_control_assert(phy->por_rst);
+
+ msleep(10);
+
+ msleep(10);
+ msleep(20);
+
+ /* deassert SS PHY POR reset */
+ reset_control_deassert(phy->por_rst);
@ -439,15 +386,9 @@ Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+
+static int qca_uni_ss_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device_node *np = pdev->dev.of_node;
+ struct qca_uni_ss_phy *phy;
+ int ret;
+
+ match = of_match_device(qca_uni_ss_id_table, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;

25
target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch Normal file
View file

@ -0,0 +1,25 @@
From 08c18ab774368feb610d1eb952957bb1bb35129f Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 00:52:35 +0100
Subject: [PATCH 37/38] usb: dwc3: register qca,ipq4019-dwc3 in dwc3-of-simple
For host mode, the dwc3 found in the IPQ4019 can be driven
by the dwc3-of-simple module. It will get more tricky for
OTG since they'll need to enable VBUS and reconfigure the
registers.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -174,6 +174,7 @@ static const struct dev_pm_ops dwc3_of_s
static const struct of_device_id of_dwc3_simple_match[] = {
{ .compatible = "qcom,dwc3" },
+ { .compatible = "qca,ipq4019-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "cavium,octeon-7130-usb-uctl" },

177
target/linux/ipq806x/patches-4.9/850-soc-add-qualcomm-syscon.patch Normal file
View file

@ -0,0 +1,177 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -70,6 +70,13 @@ config QCOM_SMSM
Say yes here to support the Qualcomm Shared Memory State Machine.
The state machine is represented by bits in shared memory.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on QCOM_SMD
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL 0xb0
+#define TCSR_USB_HSPHY_CONFIG 0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+ writel(val, base + TCSR_USB_PORT_SEL);
+ }
+
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
+ }
+
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+ u32 tmp = 0;
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+ dev_info(&pdev->dev,
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+ .driver = {
+ .name = "tcsr",
+ .owner = THIS_MODULE,
+ .of_match_table = tcsr_dt_match,
+ },
+ .probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0 0x1
+#define TCSR_USB_SELECT_USB3_P1 0x2
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII 0
+#define TCSR_ESS_PSGMII_RGMII5 1
+#define TCSR_ESS_PSGMII_RMII0 2
+#define TCSR_ESS_PSGMII_RMII1 4
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
+#define TCSR_ESS_PSGMII_RGMII4 9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG 0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
+
+#endif