2007-02-04 21:18:10 +00:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*/
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#ifndef AR5312_H
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#define AR5312_H
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#include <asm/addrspace.h>
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2007-02-15 21:52:13 +00:00
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/*
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* IRQs
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*/
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#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
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#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
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#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
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#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
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#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
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2007-02-04 21:18:10 +00:00
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/* Address Map */
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#define AR531X_WLAN0 0x18000000
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#define AR531X_WLAN1 0x18500000
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#define AR531X_ENET0 0x18100000
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#define AR531X_ENET1 0x18200000
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#define AR531X_SDRAMCTL 0x18300000
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#define AR531X_FLASHCTL 0x18400000
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#define AR531X_APBBASE 0x1c000000
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#define AR531X_FLASH 0x1e000000
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#define AR531X_UART0 0xbc000003 /* UART MMR */
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/*
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* AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
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* should be considered available. The AR5312 supports 2 enet MACS,
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* even though many reference boards only actually use 1 of them
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* (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
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* The AR2312 supports 1 enet MAC.
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*/
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#define AR531X_NUM_ENET_MAC 2
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/*
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* Need these defines to determine true number of ethernet MACs
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*/
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#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
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#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
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#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
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#define AR531X_RADIO_MASK_OFF 0xc8
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#define AR531X_RADIO0_MASK 0x0003
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#define AR531X_RADIO1_MASK 0x000c
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2008-04-20 06:40:36 +00:00
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#define AR531X_RADIO1_S 2
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2007-02-04 21:18:10 +00:00
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/*
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* AR531X_NUM_WMAC defines the number of Wireless MACs that\
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* should be considered available.
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*/
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#define AR531X_NUM_WMAC 2
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/* Reset/Timer Block Address Map */
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#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
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#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
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#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
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#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
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#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
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#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
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#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
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#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
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#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
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#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
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#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
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#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
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#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
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#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
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#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
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/* AR531X_WD_CTRL register bit field definitions */
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#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
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#define AR531X_WD_CTRL_NMI 0x0001
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#define AR531X_WD_CTRL_RESET 0x0002
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/* AR531X_ISR register bit field definitions */
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#define AR531X_ISR_NONE 0x0000
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#define AR531X_ISR_TIMER 0x0001
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#define AR531X_ISR_AHBPROC 0x0002
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#define AR531X_ISR_AHBDMA 0x0004
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#define AR531X_ISR_GPIO 0x0008
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#define AR531X_ISR_UART0 0x0010
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#define AR531X_ISR_UART0DMA 0x0020
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#define AR531X_ISR_WD 0x0040
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#define AR531X_ISR_LOCAL 0x0080
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/* AR531X_RESET register bit field definitions */
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#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
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#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
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#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
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#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
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#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
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#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
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#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
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#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
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#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
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#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
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#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
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#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
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#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
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#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
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#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
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#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
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#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
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#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
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#define AR531X_RESET_WMAC0_BITS \
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AR531X_RESET_WLAN0 |\
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AR531X_RESET_WARM_WLAN0_MAC |\
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AR531X_RESET_WARM_WLAN0_BB
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#define AR531X_RESERT_WMAC1_BITS \
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AR531X_RESET_WLAN1 |\
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AR531X_RESET_WARM_WLAN1_MAC |\
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AR531X_RESET_WARM_WLAN1_BB
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/* AR5312_CLOCKCTL1 register bit field definitions */
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#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
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#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
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#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
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#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
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#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
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/* Valid for AR5312 and AR2312 */
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#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
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#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
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#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
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#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
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#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
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/* Valid for AR2313 */
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#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
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#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
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#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
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#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
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#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
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/* AR531X_ENABLE register bit field definitions */
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#define AR531X_ENABLE_WLAN0 0x0001
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#define AR531X_ENABLE_ENET0 0x0002
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#define AR531X_ENABLE_ENET1 0x0004
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#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
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#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
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#define AR531X_ENABLE_WLAN1 \
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(AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
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/* AR531X_REV register bit field definitions */
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#define AR531X_REV_WMAC_MAJ 0xf000
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#define AR531X_REV_WMAC_MAJ_S 12
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#define AR531X_REV_WMAC_MIN 0x0f00
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#define AR531X_REV_WMAC_MIN_S 8
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#define AR531X_REV_MAJ 0x00f0
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#define AR531X_REV_MAJ_S 4
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#define AR531X_REV_MIN 0x000f
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#define AR531X_REV_MIN_S 0
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2007-02-16 09:23:15 +00:00
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#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
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2007-02-04 21:18:10 +00:00
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/* Major revision numbers, bits 7..4 of Revision ID register */
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#define AR531X_REV_MAJ_AR5312 0x4
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#define AR531X_REV_MAJ_AR2313 0x5
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/* Minor revision numbers, bits 3..0 of Revision ID register */
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#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
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#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
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/* AR531X_FLASHCTL register bit field definitions */
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#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
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#define FLASHCTL_IDCY_S 0
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#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
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#define FLASHCTL_WST1_S 5
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#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
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#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
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#define FLASHCTL_WST2_S 11
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#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
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#define FLASHCTL_AC_S 16
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#define FLASHCTL_AC_128K 0x00000000
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#define FLASHCTL_AC_256K 0x00010000
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#define FLASHCTL_AC_512K 0x00020000
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#define FLASHCTL_AC_1M 0x00030000
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#define FLASHCTL_AC_2M 0x00040000
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#define FLASHCTL_AC_4M 0x00050000
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#define FLASHCTL_AC_8M 0x00060000
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#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
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#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
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#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
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#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
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#define FLASHCTL_WP 0x04000000 /* Write protect */
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#define FLASHCTL_BM 0x08000000 /* Burst mode */
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#define FLASHCTL_MW 0x30000000 /* Memory width */
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#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
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#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
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#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
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#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
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#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
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#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
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/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
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#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
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#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
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#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
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/* ARM SDRAM Controller -- just enough to determine memory size */
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#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
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#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
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#define MEM_CFG1_AC0_S 8
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#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
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#define MEM_CFG1_AC1_S 12
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/* GPIO Address Map */
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#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
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#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
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#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
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#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
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/* GPIO Control Register bit field definitions */
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#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
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#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
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#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
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#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
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#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
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#endif
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